Daewon Ha: Sustainable Future Semiconductor Industry by Innovative Technologies

okay uh why don't we go ahead and start everybody's sitting on this side that's uh okay um wait one one Eli is coming okay so let me uh sorry all right it's my great pleasure and honor to uh introduce the speaker today uh Dr Dewan ha he is uh one of our own Berkeley uh device group uh alumni he was uh got his PhD here in 2004 uh um in two th before that he actually worked at Samsung from 1995 to 2000 uh before he came for a graduate study here at Berkeley and uh then uh graduated and went back and now he has been at Samsung now for for all that time and he is currently the um uh leader of the device uh Advanced device uh transistor structures at uh at Samsung uh which is uh uh one of the leading uh organizations in this area and they do terrific work as we learned about this week at iedm so it's my great pleasure to welcome Dewan and uh introduce his uh talk as you can see on the title I won't bother to read it and uh please yeah uh thank you very much professor buer and yeah good afternoon uh I am Dean ha and from Samsung electronics and first before I starting my like a talk I'd like to sinc uh express my sincere gratitude to the professor chaming H my research advisor and also the the S gratitude the pro Professor Jeffrey Booker yeah he is also like advising me and for inviting me as a colloquium speaker of today yeah I'm also quite sure that this collum will be a starting a stepping stone for us in the semiconductor industry and Academia to make a bright future of semiconductor together so now let me start my presentation and today uh I'm going to talk about the uh present the following agenda the sustainable economic growth of future semiconductor industry by Innovative Technologies transforming uh p challenges into growth are opportunities okay uh I will cover three topics in part one I will discover opportunities of semiconductor industry and read by digital transformation or DX and in part two I will exam the main challenges facing semiconductor technology today and efforts to overcome the overcome them through technological innovations and in part three I will present the paradigm shift in semiconductor manufacturing for a sustainable growth of semiconductor industry and throughout the history civilization has been marked by numerous revolutions each profoundly altering the way the information is is shared and accessed since the dawn of writing with the invention of the Kun form writing system in ancient surian with uh around 3,000 BC the exchange of knowledge has evolved from spoken word to the use of written documents bringing about the fundamental change in our ability to preserve and disseminate information and the 20th century ured in groundbreaking advancement in electricity and electronic devices initiating the digitalization of information which laid the foundation for another revolutionary era of digital transformation in the 21st century from PC to smartphones and to the recent explosion of iot 5G and AI such as chat GPT we have witnessed an precedent surge in the creation of Digital Data and that is we are entering a new era digital transformation a transition that has been deeply penetrated in our into our daily lives at the basis of these grand openings of the new era both hyperconnectivity and Big Data creation lie at the heart of it shown in the left chart just a second yeah shown in the left chart the number of connected devices is is growing rapidly by 2025 approximately 80 billion devices which is 10 times more than the world population will be connected to each other and furthermore it will be staggering to see the total amount of data generated by this hyperconnectivity for example a 97 Gaby of data was generated in 2022 and it is projected that this figure will be doubled in only three years soaring to 181 Gaby and this weth of information collect Ed from Edge devices such as smartphones is fured into Cloud systems for processing regeneration and storage and therefore in digital transformation era high performance Computing capability and large scale storage capacity are required for both EDG devices and data centers leading to the to the continuous growth of semi conductor industry and as we went through the pandemics we all realized that information Technology based on semiconductor industry is indispensable for our daily lives and we are able to work study and play in the online platforms all powered by small semiconductor chips and the global market for Semiconductor was value Ed at 900 uh 590 billion US do in 2021 and the market is expected to grow continuously and an an average rate of 7% and reaching 1 trillion US Dollar by 2030 although the global semiconductor industry is currently in downturn due to stagnant economy the semiconductor Market is ready for a rebound and it will be expected to grow continuously grow in the mid to long term and this growth will be ped by new applications such as iot augmented reality and virtual reality and smart cars and Robotics and these applications will be further evolved with the development of AR arcial intelligence such as large language model and large language model based AI is expected to create numerous new use cases across all Fields including it energy and transportation Commerce finance and Beyond and in summary as we go deeper into the era of digital transformation I'm quite sure that that we will witness the immerse potential of the semiconductor industry so over the past 50 years Global semiconductor market and its stringent requirements have been satisfied through in ration technology with which we were able to have realized ever demanding higher performance as well as ever demanding lower cost pop transistor and for example compared to 1970s microprocessors today's microprocessor speed increased by 100,000 times and the number of transistors per Vapor increase by almost 10 million times and at the same time the cost per transistor per Hertz was reduced by 46 % every year and however semiconductor industry is currently facing many challenges and these challenges stems from the limitations of conventional mization Technologies and unfortunately leading to a higher investment size as a result it gives us a great concern on economic of semiconductor especially for manufacturing invest intensive sector so now it's time to look at the technological challenges as well as the Relentless efforts to address them in key two key building blocks of semiconductor industry data processing which is represented by Logic transistors and the data storage which is represented by Dam and nand so up to now the evolution of logic DRM and nand has been achieved by self-fulfilling prophecy the Mo's role and which has been guiding us toward the ever demanding high density high performance and low cost however as we March forward to the physical limits of devices the landscape for uh landscape poses ever everever mounting technological challenges and in order to move forward Beyond these barriers technological innovations span from technology structures and the materials and Fabrication processes are inevitably needed as we did in the past and in addition recent challenges require not only technolog iCal breakthrough but also new ways of approaches such as dtco Design Technology Co optimization and stco system technology Co optimization and furthermore at the same time and concerted efforts across the all stakeholders of semiconductor industry are imperative because only through all encompassing Innovation we can overcome these technological barriers and navigate into the Uncharted future so in the following slide I will talk about the past present and future of semiconductor uh silicon especially silicon Technology Innovation from the perspective of data processing and data storing and first I will discuss the Innovations of rogic Technologies for data processing high performance and low power and small area with low cost have been the driving force behind this Logic Technology Innovation however around the tun of Millennium Simo scaling reached an inflection point where power performance gains from geometric scaling so the miniaturization started to diminish and physical limits emerged the application of high Kade dialectric and merat and embeded silicon germanium sour grain has made continued simos scaling possible in addition to Innovative materials structural Innovations like fin pets and ambis pet has made simos scaling further down in 2014 Samsung pound was the first company in introducing fin Fest as its 14 nanom do with extremely ultraviolet is Ry simply saying euv SOS scaling pushed down below 10 nanometer and now SOS is ready for three 3 nanometer technology node and Samsung is in mass production of 3 nanometer using the world first gate all around transistors MBC fat meaning multi Bridge Channel fat and as Illustrated in the TM image in the in the center M pad provides maximum electrostatic control of the channel because of the gate or around so that the MBC fat improves the transor performance and at the same time MC fat can enhance the performance further by stacking more additional Channel layers however as we go beyond 1 nanometer physical and technological challenges appear again and generally speaking the smaller cell size smaller standard cell area the better the logic transistors and obviously a smaller standard cell area can be achieved by scaling the standard cells with the x-axis and the height the Y AIS and why while the width of the standard cell is determined by CPP the contact poly pitch which is the lateral distance between the gates the height the standard cell height is mainly dependent on minimum metal pitch so in order to scale down the CPP we need to reduce the dimension of either gate lengths or contact size however the decreasing the gate length induces large leakage current due to short chel effects and decreasing the contact Dimension increases large contact resistance and on the other hand in order to scale down the standard cell height we need to reduce the metal pitch therefore metal width and this inevitably increases metal resistivity due to the non-trivial surface and grain boundary scattering therefore critical challenges in logic transistors are reducing the sh effects and improving the contact resistance and interconnect resistance and in order to overcome these challenges let us look into Innovative approaches by focusing on the structures and metal materials so one approach to decrease the gate lengths without suffering from Channel facts so the the other approach the the to for the cppp scaling first approach is to decrease the scale lengths without supporting the sh effects and the other approach is that the dimension of the gate length decreasing it decou that from the M Mo context from the structural point of view and first let me start the gate length scaling first as as we mentioned previously MBC fed provides the excellent ceral static control of the pot Channel potential so that we can push down the channel lengths further and the other approach is the adapt a no Channel material so two-dimensional TMD transition metal diogenite material as a channel which is only one monor Ray thi and the ultimate thickness of the channel and this can provide the ideal property of the channel such as high mobility and uh extremely small parastic capacitance due to its coming from the like a thickness on the other hand the bical transport F fat with fat it can stand out for its ability to place M Mo contacts out of plane not in the same plane plane the outdo plane to minimizing the contact resistance and the sh effects however uh this BCT pad PT pad suffers from the the maximum frequency benef maximum frequencies therefore higher current driving capability and BT control needs to be further explored for the standard cell height reduction so in order to scale down the standard cell height and while maintaining the standard back end of rine scheme we should like utilize the backside interconnect technology as the name the backside interconnect or backside PDN power delivery Network implies we can utilize the wh backside as interconnect platform for Signal lines and power Lin lines so that we can push the standard cell height more effectively realizing a smaller smaller cell height and then the MOs and pmos isolation space p is not a trivial like active T is not an active device area and not that trivial will be squeezed as much as possible as shown in the Poke shet Pok shet structures and ultimately OS and pimos isolation area can be completely eliminated by stacking the OS and pimos so stacking just the MOs on top of the pmos like three dimensionally stacking the transistor and summarizing the future Logic Technology Innovative device structures like uh like a 3D stack fed and Fork shet and new materials for device Channel like a TMD and advanced metallization scheme like a backside interconnect and uh OS and pmos stanking will continue the standard cell area and now I will discuss the Innovations in memory technology for data storage oh yes before you leave that can you show us how the V are made through the Silicon wafer how dense they are and so on uh there a tsv yes yeah tsv is a just a like a through S be and so the density might be like 50k less than that the number of the uh tsbs is a quite like ,000 per square cimet no you know chip so I think that around that yeah soing about back so the size is like quite small for this case it's like a TSB is a micrometer size at least but this one is like 10 nomer or 100 so the dimension contact Dimension is quite like a huge gap between the tsv and the this kind of a BS so this is much more advanced one and this is not like uh we coming soon like from the Intel mention like uh next year probably but this one is above that one so beyond that one so I think the density of this one yeah density is how much uh think that right right right so like a billions of there right right how do you make the holes for this this is just a conventional like a liography and the edge like a right right so sitting down the Silicon first and then just flip it and then just patterning it and then edch it so I think that yeah those are the things but this is just a typical like a process integration scheme but needs to be more for like explored how we can like effect cost effectively fabricate these things okay okay so let me discuss the memory Technologies for data storing and dram is mainly used for highspeed temporary like a data storage for data processing in the Computing systems therefore higher density and low power consumption and higher bandwidth are always maintain main technology drivers of the dam technology and the achievement in dram over the past 20 years have been remarkable and we have continuously shun the design R by almost 60% from 35 nanome 35 nanometer to down to 14 nanometer and this comes from the Innovative structures from cell transistors and capacitors including buried cellay transistors we call it bat and Bally stacked capacitors together with n materials like high dialectric and advanced processes like euv rography and so on however pach car and technological challenges is room for scaling Beyond 10 nanom DM node so what are the critical challenges to sustaining sustain the DM scaling below 10 nanometer and there are four critical challenges and leakage current mainly due to the GLE the gate induced drain leakage and on State current of of a cell transistor and cell capacitance storage capacitance and data reliability like a low hammer and passing gate effect in the following slide let me look into the Innovative approaches in more detail by first focusing on the structural Innovations so as you shown in the left subst leakage and on uncurrent issues of conventional bcat uh very accelerate transistor structures become no longer tolerable due to process variability Innovative cell structures like bical Channel transistor BCT and vertically stacked satate transistors BS cat May provide the solutions while maintaining the process margins in BCT we can separate two contexts for for bin line and storage capacitor and place each contact outo plane therefore we can achieve the smallest D un cell area 4 F Square compared to 6 F Square in conventional B uh pcap here f means a minimum picture size and on the other hand in bcat we can place cell transistors and capacitors on the same plane to form a to form a single layer of a DM cell then stack them but Al to create a multi-ray cell arrays resembling the transition from 2D Planet land to the 3D vertical land I believe that these two structural Innovations will allow us to sustain DM scaling scaling trajectory Beyond 10 nanometer cost effectively and however we should overcome challenges in suppressing the rage current due to floating body effects and grain boundaries of a cell transistor Channel with Innovative processes and materials and there are two approaches to deal with this uh leakage current due to the floating body effect and passing gate effects and one approach is suppress leakage current by developing an ADV Advanced processes or n materials for example we can great suppress liage current by applying grain engineering therefore less grain boundaries in the polysilicon channel in order to have a sufficient cell capacitance High dialectric capacitor materials are inevitable in this respect the fedro electric will be a good material choice for the capacitor in the dam in future Dam however we should over come challenges such as variability for scaling down below 10 nanometer we need to go back in in this case we need to go back to the like a Basics and reconsider the constituent elements of a DRM cell So currently it consist DM DM cell consists of one transistor and one capacitor soall one t1c and we may achieve the smallest and probably the simplest to cell over DM by taking the capacitor away and storing a data information either inside the channel region or inside the gate F electric material and the beauty of one transistor one t f f fat the is that by partically stacking one F fat cell arrayers and we can realize the highest density of dam as much as we can in a cost effective way however we should overcome challenges such as reliability and including cycling endurance and variability which often comes with the comes from the properties of the feder electric so in summarizing the future Dam Innovative cell structures Advanced processes and materials for transistors and capacitors and number capacitor want a fat based d will scale down the DM technology much below the 10 nomer and Beyond so now let's switch the gear to the fresh and memory technology for permanently storing the data information ever demanding high density and lower cost per bit are the main technological driver of the flashh technology and therefore throughout its Evolution Innovations to land technology has always focused on the cost effectively increasing the bit density so since we introduced Bal land in 2013 for the first time in the industry the achievements in Flash for the past 10 years have been remarkable we have pav a way to continuously increase bit density of about 30% per Generation by vertically stacking more layers which mainly comes from the Innovative wiend structure and advanced Haw high as ratio contact etching processes and equipment with double stacked and cell over periphery cop structural architectures we can achieve the smallest cell volume and mitigate the total stack High height can challenges however physical and technological challenges room for stacking more than 1,000 layers of green end so what are the critical challenges to sustain band stacking Beyond 1,000 layers So currently like a 250 layers now and there are four critical challenges and these are mainly come from ever in increasing total stack height including High Asen ratio etching the Haw Edge and the mechanical stability and low cell current and interference between cells so as we stack more and more layers ensuring the structural Integrity is crucial to achieve our density goals so first let's have a look from a structural point of view as we stack more and more layers High spe racial contact Edge to form a channel hole become extremely challenging because a bical pitch of a single layer is no longer scalable therefore requiring Innovative cell structures and these are three promising candidate structures a multistack and sprit cell and trapal cell structure and in multix structure we can mitigate the required process capability for Haw Edge at the cost of additional repetitive processes and in the sprit cell the bit density can be doubled while maintaining the total stack height however there will be an additional Haw Edge is required on the other hand the Trap cut cell vertical pitch over single layer can be scalable by cutting on charge TR layer we can greatly suppress the interference between neighboring cells however these structural Innovations can mitigate the challenges of the stack height increasement but it cannot stop tal stack height increase as more layers are stacked with ongoing evolution of generations therefore aggravate the cell current and mechanical instability so we can mitigate these pressing challenges from the perspective of number processes and materials to tackle the issue of low cell current there are two approaches first is uh grain engineering with recrystallization of recrystallization processes such as milk so metal induced lateral crystallization we can increase the grain size of Channel po silicon achieving a significant Mobility enhancement and second is a naal oxide semiconductor Channel materials which have higher Mobility than conventional poly silicon Channel and the uh however this comes with the challenges of controlling memory window and Ensure the reliability on the other hand in order to improve the mechanical stability we need low stress and low resistivity metal films without sacrificing the excellent step coverage and eventually we may pursue the Slow Down slow down the total stack heide increase so to this and we need to decrease the operation voltages such as program and eras So currently like uh 24 20 more than 20 BT but by adopting the Innovative non-charge based storage devices such as fer electric or Regis memory devices in summarizing future flash Innovative cell structures and also the advanced processes and materials for cell transistors and Innovative non-charge based memory devices will enable flesh to St over 1 1,000 layers and Beyond so in the landscape of the semiconductor technology the relent R March of progress brings Force unparalled Innovation however with these strides comes on undeniable challenges the escalating the cost of development so a particular concern are the stiff expenses associated with introducing Cutting Edge fabrication method and advanced technology and these factors has contributed to a pronounced surge in investment costs prompting the need for the Holistic Solutions that incompass both technological and the manufacturing fields so Innovation isn't limited to the technology breakthroughs alone and firing uh idea is also sprouting within the field of a Fab operations and I'd like to sh sh shed right on a concept that holds immerse promise for our industry on mization on revolutionary manufacturing approach on modula Fab stands as a departure from the traditional continuous production processes and rooted in the concept of modular semiconductor devices this method brings Innovation to the Forefront of Fab operation and one of the Prime advantages is that its ability to sustainably cut down the production M timelines by creatively shortening the manufacturing periods compared to the conventional method this like a modula FB offers a dynamic response to the ever ever increasing the demand of the time to Market so moreover the modula Fab has the potential to induce significant reduction in fabrication cost achieved through the streamlined exclusion of recycling and verification of the modules the requ that requires for the development this approach ures in an era of drastic drastically cut down the cost fabrication cost in the dynamic Realm of the semiconductors modularization and the pursuit of number approach are viable So modularization within the context of each product involves dissecting the intricate processes into manageable modules and using a bonding process and establishing a dedicated Fab operations for these modular units holds the potential to not only slash the manufacturing timelines but also the unlock the substantial cost efficiencies so this slide presents an comparison between the existing production method and modular semiconductor production with the extended with the estimated turnaround time tat and by implementing a modular Fab operation remarkable Improvement in tat are evident across the logic DM and flashh flashh N sectors and these Improvement provide significant benefits including the inest market responsiveness and substantial reduction in manufacturing cost so important ly this approach mitigates the challenges of Rapid investment cost escalation associated with the conventional method and this can fve the way for sustainable growth in the semiconductor industry okay for a sustainable future of semiconductor industry I discussed the pivotal law of semiconductors as a Vanguard of digital trans transformation era and presented the Holistic Solutions that Encompass technological and the manufacturing Lums and this journey will continue and I Envision that the thriving future of mankind where the power of semiconductor Innovations benefits the world and where our Innovations knows no bound and thank you very much thank you very much for this very uh inspiring presentation uh there are questions go ahead sa so very nice very nice presentation I have a couple of questions um yeah a couple of questions um the first one uh if you don't want to answer I understand but any um any um buper number you can mention for the average CPP the contact poly pit uh the current one or yeah I mean one of the I think yeah everyone knows that so like currently like this is around like 50 50 50 nanometer and the limit for the like you are change you are facing the challenge will be around 40 okay so below 40 is definitely very very difficult I don't think that'll be possible for like using a silicon so new material new channel material sure we be the we'll have a chance to below the 40 to break the war CPP ask him one more yeah so one more question about the modular Fab line that that's very interesting um one question I have is it looks like that you are talking about um parallell developing front line um and the uh back end of the line um together and you know uh we kind of learn about um the process you know the traditional processing that the front end of the line is done and then you think about back end of the line so I'm wondering if you can comment on what changes is are necessary to kind of develop those two things in parallel uh you know are are there challenges or is kind of understood now how to do that and I think that this is just like initial like a concept so it is not realized the one but I I think that this this is the way we should go otherwise the yeah the cost and the investment goes like a shooting like that so I don't think no one can have a benefit and the word the community may not have a benefit from the Innovative Technologies so I think that this is the way we should go into the industry so we need to like develop more ideas to there thank you yeah I mean so just following on what say if i' ask yeah so is the idea to like do 3D Integrations where you stack these things on top of each other is that what you envision with this modular so with this modular approach is the idea to do 3D stacking you know or are you doing these you know like separately in stack I mean so so yeah I'm just kind of curious like how how you envision that uh that modular approach if you're doing the back end of the line separately then they I think yeah so is it like chiplet where doing 3D stacking or something of that sort or something different so that is uh something different I think yeah because for the chipet approach is like making the each chips like a small like a small portion of the chin and then just uh reconstruct the like using a vapor or some other like method but this approach is a kind of like a similar but like a not whole chips but part of the chip is like a parly like a fabricated and then just it is like using a already verified modules so and then just combine it together to make a chin it's a slight different like concept but quite similar and the other question I had so you had vertical uh you know the vertical fact you know we were saying that this reduces the the pitch scaling you so yes so what's the road map on that is that something uh so so you have the gate all around and all that stuff going on is that is that going to come after that or is it like uh yeah MH I think that put like that is a really good structure like Innovation for the like using a partical path like a partical transport path but however for the like a logic approach there are so many things I need we need to like satisfy that there are so many critic critical criteria for that but like a maximum frequency should be like should be satisfied but I don't think that be happens in the pretty F to be honest with you but those like a structural Innovative structures can be adopted in other other than the like a like memory applications it is good so especially for the minimizing the area so memory cells like Dam not fresh but Dam may have uh you you may see that kind of like structures because lateral Dimension shrink is extremely difficult for memory especially for the dam so I think that those things will be very helpful have some benefits in scaling the technology so I think that those will be happens in the D applications any other questions I I guess I'll ask a question um I'm fascinated by the uh concept of the modular Fab I've been thinking for some time that uh sooner or later we have to start to figure out how to reduce cost and uh this looks like a uh a good healthy start in that direction so I'm I'd like to maybe pursue and and learn a little more um one thing that occurs to me is that you know you use the the the term stco system technology co-optimization and I can see where in this context of this modular Fab you can really do something there uh I wanted to ask in particular if given that we are now seeing uh architectures really evolving for uh machine learning and for other things how do you see these things coming together is there is there any synergies that you can see and how we can uh you know um take advant do more stco to improve simultaneously take advantage of new art the way architecture is evolving maybe driving the architecture for machine learning uh in ways that facilitate this modular approach or anything like that wow okay maybe that's a a topic for discussion yeah that's a good topic for the like a during the like a dinner time okay yeah yeah I didn't think of much about that but yeah should right yeah well I'll ask a simpler question then about the modular if I understood uh correctly the the previous question so the the front end and back end would be perhaps manufactured separately and maybe even separate Fabs and then there would be some kind of uh assembly whether it's bonding or something else are so right now I I heard a lot of talks about wafer bonding at the IDM this week uh is that the main approach you have in mind or are there some other ideas that you are thinking uh could be uh used for this modular I think that yeah there are so many different things should be happens in there but one approach for the process point of view that is a good option just um bonding but not only for that there are so many things like a protocols how do like how many like uh current or some other things should go and go and and so the protocols and other like a uh uh approaches for the design point of view like a especially circuit yeah is also needed so but process point of view the bonding will be the yeah I think that that will be the first option so um just following up one more step uh you talked about the backside power Network earlier on now in this modular approach is it just the backside power Network or do you actually imagine you know what we consider now the the up if I could the back end on top right the the interconnects for signals uh would also maybe be another module and can you can you imagine uh bonding together you know full let's say from uh M3 up to whatever we go M10 or M12 as a uh uh as another module that would be somehow assembled I think yeah for the different approaches for the different product of course yeah but for the logic case if you have a backside PDN yeah that is a good yeah there is some some other like a boundaries we can like optimize it that might be some of them just there but the the upper stack of the of the back end uh could that be uh you know if we could get really get the registration Alignment good enough could you imagine having that be a separate module I think because the cost matters actually yeah so as long as the cost is not much increased then might be the like a way however typically the bonding like is very expensive so yeah it depends it depends like and also the depending on the like uh indust like the company they may have a different approaches sure sure so I think that totally depends on the like the company's situation Eli so what what you're describing here uh resembles something uh that was very interesting to the defense department about 25 years ago which was the creation of multi-chip modules and it sounds like it's very similar what you're describing uh uh have you heard of multi-chip modules no I don't think I okay so it's modules it's many chips many chips on a single substrate CPU right there or yeah many applications also stepping stone something called a silicon interposer which also was a a kind of a step Stone uh toward multi-chip modules I see okay thank you thanks okay if there are no further questions uh let's thank uh Dr ha for a really stimulating talk thank you very much thank you very much

2023-12-20 01:05

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