Advancing Moore's Law with Backside Power Delivery
[Music] thank you [Music] hi this is Pat Moorhead welcome back to the 6'5 Summit day two we are talking about one of my favorite topics semiconductors okay maybe it's my favorite topic and we are diving deep on some important technology that Intel is delivering not only to its internal design teams but also to its ifs customers so with that I'd love to welcome Ben and Eric welcome first time six five thanks Pat great to be with you today nice to meet you Pat we've had some awesome Intel folks here on either the 6'5 podcast 6'5 Summits heck we even had uh Pat G who he refers to me as a little Pat and I refer to him as big Pat who kicked off The Summit a few years back and I'm ready to talk about some incredible semiconductor technology maybe a great place to start uh maybe Ben you can kick this off talk about what you do for the company and then Eric you can go afterwards all right uh thanks Pat Uh yeah I'm uh vice president for technology development at Intel responsible for our technology program so we have our technology roadmap and I'm responsible to make sure that the different programs stay on track and we can deliver the future is good future is important I'm Erica I'm an Intel fellow I work in the design organization to align the technologies that Ben delivers and figure out how we take that technology and develop our next Generation products I love that you know many times people forget just how long and it how long it takes to create a design take it into manufacturing but by the way you're everybody's working on all the transistors and all the Fab Technologies uh along the way it truly is impressive so why don't we start uh Ben uh with you one of the big technologies that Intel has been talking about is this concept of backside uh Power delivery can you talk about why this is important and how this relates to Moore's Law yes of course so uh the way we built our chips is we start with the tiniest features the transistors then layer by layer we add wiring to it from Tiny wires to slightly less tiny wires and currently these wires were fill two um two applications one is we have the signal wires that uh connect the transistors with each other and within within die connection and we have the power wires that connect the power supply to the transistors themselves as we scale down the size of the transistors the wires also have to get smaller and smaller and over time become more and more a bottleneck for the performance and the scaling of the transistors what backside power delivery is doing is it's taking the power wires from the front side and putting them on the back side of the wafer this gives us a lot more room for the front side wires to be bigger while still enabling the scaling of the transistors giving us a lot more performance and the power delivery is a lot more direct to the transistors giving us a higher performance in addition yeah that's great so uh Eric uh what does this mean to uh the chip right and we've talked about the technology the backside power delivery kind of separating the power from the signal but what does that mean for the chip the power or the density uh and the uh and the performance so first of all the backside metal gives us the best possible power delivery scenario we can have on chip and and those losses are substantial and by eliminating those losses we get lower power and higher frequency right but the second aspect of it is by removing the power from the front side Metals Ben mentioned we get bigger interconnects well we can use those bigger interconnects to improve our frequency to reduce our switching capacitance which is safe power and enable smaller area all at the same time right you know to put a little uh quantitative data into it you know we were able to rebuild our core with this technology and get 90 cell utilization a 30 reduction in in power supply losses and almost a six percent frequency Improvement just from a rebuild with no other changes I love it when you uh guys talk like that um so there are other ways to do uh backside power right uh I do a lot of research on Intel but I I do a lot of research on on the industry itself so I'm curious it's probably a question uh for Ben how does power via Intel's power via approach how's it different from other ways that that people are approaching this and why is it better yeah Intel's power via is a direct connection to the contact of the transistor from the backside this gives us a very low resistance part from the uh from the bumps to the transistors themselves and and further improving performance but it also does not go through the lower metal layers like some of the other uh Power backside power Delivery Solutions that are out out there and what this does is it frees up the lower metal layers and does not consume any wiring for power delivery and as Eric mentioned this allows us to widen the the pitch of the lower back end layers and with this one we can achieve multiple things first of all we get better performance because you have fatter wires and can deliver the signals better but it also reduces the requirement for very aggressive scaling of those layers those the scaling of those layers first of all it's very expensive and the the cost we are saving from not being that aggressive more than offsets the cost for actually doing the entire backside power delivery process and in addition less scaling also means it's a more stable process and has less risk for yield no that's good and you know um having been in and around uh semiconductors for over 30 years it's funny I was a it was a specker and a buyer of semiconductors for an oem worked for a semiconductor company for a long time and here I am last 12 years uh being an analyst to the semiconductor industry it really all comes down to delivering PBW for certain workloads right and I think as the industry has progressed there's been more of a focus on specific uh use cases and I'll direct this question to you Eric are there any specific applications workloads use cases where backside power delivery uh really um shows its true colors sure Pat um with backside power delivery one of the the key things is it delivers in performance Improvement across all the workloads but specifically the ones that take high power the ones that drive changes in power consumption in the part those would be things like AI Graphics high performance Computing and even gaming those workloads in particular backside power truly shines that's awesome and by the way that's that's where the ball's headed I mean there's no uh there's no doubt all the research that we do and it's not just the conversation and you know the big fireworks that are going up this is this is where we need uh this type of of enablement so um Ben I understand um that you've created a very special node and a test chip for power via to validate all these performance expectations for the workloads that that Eric talked about uh and I hear uh you're doing very very well and by the way I if I track you on nothing else it's like five nodes in four years um can you tell us more about the test that you're exceeding expectations on and maybe talk about some of the results and and the metrics that you're that you're basing that off of yes of course so when you look forward the the fourth and fifth note we are delivering Intel 20a Intel 18a those notes we have two big Innovations we're putting in power via and ribbon fed one thing we wanted to make sure is that we understand and debug the power via process ahead of ribbon Fed so that we don't have two big problems to solve at the same time all right so we created a node where we took our Intel 4 process and added power VR on top and there were four main items we wanted to get out of this test chip and our product like test ship as well first we wanted to make sure we developed the process get good yield get good relability understand whether the any shifts in device parametrics and fix those so that one we have done successfully with our test ship second as soon as you put backside metals on the chip it does change your abilities to do chip level debug since many of the techniques required to have access from one side with this test ship we could validate the new technologies for debug that we have developed and validate that they're working and that we can find design bugs and and also process defects the um the the the the next item that we wanted to make sure is uh that we understand The Thermals uh as soon as you also put wires from both sides of the transistor we wanted to make sure that the models we have for how thermals behave are accurate and that we can develop and test solutions to address any concerns with thermals and that also we have done and we have now developed uh solutions that we can give our customers to to deal with the thermals on backside power delivery process yeah so a lot of these decisions are all about risk and you know de-risking power via from 20 angstrom uh seems like a good idea but uh why we want to combine the two and maybe just not offer them kind of further down the road I mean maybe this is an obvious answer but you know I have to ask Ben yes uh no this is good the the fourth item from the list I just mentioned is we wanted to make sure we can demonstrate the intrinsic value proposition of Power Wheels so overall when you look separated in a way yes so but if you look at it both the power VR and the ribbon fed provide a significant value proposition that we want to give to our customers as soon as possible so uh currently both of these look very good in our development lines and um we we wanted to make sure that we can de-risk those and make sure both of them are ready but give both of them to our customers as soon as we can and uh overall what we are seeing is whenever we have a new node there's a lot of new development a lot of new IP that we need to develop and we wanted to make sure that our design Partners have the full package so that they design NRP once and can use it for all our into well 28 Intel 18a products no that's good I get it now thank you uh so you know it really does take a village and you know with Intel supporting industry standard Eda tools uh out there that translates to having to support uh special valuable features like backside power uh what what do the Architects that ships to ship designers out there uh need to know about it is the industry ready is is it there where are we on this map maybe that's Eric's that's that's for you sure we we have you know full what I'll call Basic Eda support from from from the large vendors today um by no means have we hit the point where it's delivering the absolute best so we're still working with the vendors to improve uh the performance of the results and the capability of the results and in a few places we rely on design methodologies to cover the holes in the future where we expect tool an Eda vendor optimizations to help us out uh potentially in things like signal shielding and thermals that Bennett mentioned there are some opportunities still but um with the packages we have today we're able to leverage the value the core value of backside metal and power via with the vendor support we have today I think that's good news and by the way I give Intel a lot of credit for the support increased support of Industry standard uh tools I can tell you from experience it took a lot it takes many years uh to to shift uh to that and you have to particularly when uh when you want to be a leading uh Foundry which I know ifs wants to be to other companies that might be using different tools so um let's talk um Eric another question for you from an ifs business so an Intel Foundry business perspective uh what is the potential uh and business potential competitive landscape for power via and I know it's got to be hard to to put that all in one feature uh but it but it does seem like it is one of the bigger differentiators that uh obviously internal Intel designs could take advantage of but but you know as importantly or even more importantly uh ifs customers right um so when we look we look at a feature like power via first of all why are customers buying uh the technology in the first place right it comes down to Performance power consumption an area and power via really addresses all three of those areas very directly we get significant improvements in our ability to deliver power and power consumption we get the frequency improvements that we discussed and we also are getting you know significant improvements in areas this kind of leaves us a note ahead from the results of power via versus what competition is offering in the same space right so from a customer perspective it's delivering on point for what they're looking for right combined with the Eda support right we can deliver a package that enables them to bring this to Market with their designs in a quick and efficient manner do I love it isn't it funny uh after 40 or 50 years in this industry it's like it's PPA it's always been started off with PPA and it's still PBA we might be doing it differently we might be measuring a little differently it might be more systemic uh than at the my chronic or subatomic but it's still all about PPA I love that what's old is new what's new is old gentlemen I've really enjoyed this uh conversation but I wanted to hit you up with one uh one final question here does backside power and gate all around kind of show that Moore's Law isn't dead uh and listen I you know I've been hearing about the death of Moore's Law forever but I wanted to make sure you're able uh to weigh in and kind of my my core layer to that is is what are you thinking Beyond these new transistor Innovations and Ben why don't we start off with you yes muslore is alive and well and uh the um the the the two innovations that we have power via and ribbon fat which is our version of gate all around are a critical inflection point for our aggressive five notes in four years roadmap and getting back to process leadership by 2025. yeah from my perspective right these are two steps in a in an ecosystem to get me to a trillion fets in a package right we're looking at 3D constructions disaggregation technology optimizations for functions including memory and power delivery much like what power via and backside metal provide and this is a step on the journey to get there and we see a good road map going forward of Technologies like these to get there yeah and coming back to the roadmap that Eric just mentioned uh first of all ribbon fed and power via the Innovations we have from that that will carry us for the next two process node at least and then we have many very interesting options in our Labs we're testing like cfet or new channel materials that Propel us further going from there yeah well um it's our job to leverage the technology that Ben delivers now and into the future and we're doing that through several methods including taking the new technologies and combining them with old Technologies or specialized Technologies right so one of the things I'll highlight is specialization whether it's memory power delivery those kinds of things are becoming a larger role and Ben is enabling these features for us each generation something new is being added particularly with power via it's a power delivery technology but he's going to give us more magic in the future that's what we need just board magic to get us uh to get us forward here and it is so funny uh I'm just always astounded at the amount of research uh the amount of engineering hours that go into making this happen and listen every every decade I hear that oh we've hit a wall right but somehow the industry through sheer Brilliance a tremendous amount of of investment keeps moving it Forward because the success the industry success and quite frankly Intel's success is Paramount to the future of of of all of these Innovations uh I you know for one love to see all the competitive Foundry capabilities uh bringing uh brought to the table and I'm not confused at how much investment that takes uh how different that takes to be able to serve different types of customers uh for ifs and obviously just you know to serve a really big ifs customer the internal Intel design teams happens to be a an important one as well so it's good to see Intel bringing out some very demonstrable and differentiated Technologies I've been aware of power via I think going on four to five years now and that's just how long I mean you didn't even just start this though you started a lot longer and it's just it's a almost like a miracle that some of these Technologies uh come to the table Ben and Eric I just want to thank you again for coming on these five Summit 2023 day two and really making this program more exciting you know I love Seneca doctors our audience loves semiconductors and we love doing the double click learning about new technologies like backside power through Intel power via so thanks again for coming on yeah and thanks for having us uh Pat it was great to talk to you uh about power via and then what the future brings yeah yes Pat it was an absolute pleasure love to have you back on uh to learn more about it maybe even do a Victory lap as we get uh closer to uh full production sounds like a great plan so I want to thank everybody for uh tuning into this segment of the six six five Summit day two semiconductors and we are just absolutely doing a double click on cool technology backside power uh delivered by uh Power via Intel uh we are hopeful as an industry that it will deliver tremendous benefit to not only Intel semiconductors but also ifs ifs customers so hey stick around we're going to be talking a lot more semiconductors here in day two if you missed day one it's okay it's uh it's on record it's on time time lapse go back and check it out and also check out day three because we're going to be interviewing uh companies that are the most relevant in the technology industry and their Executives so take care thanks again foreign [Music]
2023-07-06 14:52
