hi there thanks for being with us today my name is carmina and i'll be your i'll be your host for this part but we actually will have a master of ceremonies and i'll talk to you about that so welcome to the new technologies for sipi simulation and pathwave ads 2021 virtual seminar so i'm going to introduce tim wang lee who is our master of ceremonies and tim you can take it from here well good morning everybody good morning carmina thanks for the introduction today it's a little different format let me introduce you to today's signal integrity and power integrity demo challenge today we're going to have four contestants and four distinct demos and only one survivor i mean only one winner all right one winner what does winner get the one winner get to keeps his or her job and of course i'm i'm kidding here it's only bragging right so we're talking now you might be thinking well how about the loser what is the punishment for the losers for one is no time off for the rest of the year but realistically we're gonna restrict your beer intake for the next three weeks so we're gonna have a strict monitoring system to check your beer intake your blood alcohol level now now the rules for for deciding who survives i mean who wins is a a minute demo challenge format in that demo the contestant has to show why you should care about the demo and the five minute of demo and take away you know what what's what's so important so all together five minutes i'll have a timer and at the same time i'll make sure that you get to vote you get to vote so the years are the rubric from a scale of one to five did the demo show you why you should care from a scale one to five is it clear what the problem the demo is solving so these are the rubric now before we start the competition i want to introduce our four contestants on deck namely is mr stephen we have heidi we have vandana we have heesoo and do a little quick introduction on their name their role and a fun fact about themselves the first one is mr stephen slater stephen please give a quick introduction of your name role and a fun fact about yourself take it away stephen hi there guys yeah so um my name is stephen slater i'm the si pi product manager uh fun fact about me is uh during uh work from home i decided to try to learn how to surf and i guess i kind of figured that if i changed my hair color uh i might do a better job at surfing so that's it for me well changing your hair color to to to get better at surfing is as much as changing the the color of my computer to get it to work faster but don't take my word for it next up is miss heidi barnes heidi would you like to do so to do an introduction of your name role and a fun fact about yourself yeah do we have heidi how do you how do you really like there we go underwater i am i'm holding my breath over here tim we'll get to that fun fact heidi barnes here and i am the pathwave ads power integrity product owner and the fun fact that i have to share today is that my favorite sport is underwater hockey and you get bonus points if you've actually heard of that sport and i definitely can hold my breath longer than anybody on this hsd team back to you tim thank you heidi and let's hope you're you're you keep above water for the rest of the presentation the third one up on deck is vandana would you do a little name roll and fun fact about yourself hey everyone vandana wilde here i'm a product marketing engineer for high speed digital and a fun fact about me is that i like to lift heavy weights and can currently dead lift as much as i weigh well thank you vanana i hope i can also lift a lot especially the weight of the world final last but not least mr heesoo lee please do a quick introduction of your name rule and fun fact about yourself heesoo take it away all right sounds good my name is i'm the product owner for a memory in a product and fun fact on myself i'm going through probably middle age crisis so some people may not notice me because last year i had a long hair with a ponytail and then now i have a more like a buzz cut so the victim of this you know interesting part is my hair that's on me all right all right the hair is the victim i think there's a connection here between the blonde hair better serving and then haircut for better simulation we'll see what uh what the haircut would bring to the table now be before we do more i want to show this uh this minute eight minute challenge demo format again so it's eight minutes and we have to show why you should care where the customers what the audience should care and the demo and the takeaway and the first one on deck will be mr stephen with the blonde hair don't care this even please take it away with your eight minutes and i will start the timer all right guys so hello i'm gonna actually try and cram two demos into the one time limit so let's get started uh the first thing is when you lay out a pcb board there's so many traces and we don't have time to electromagnetically simulate them all so how are you going to verify that the impedances are correct and because there's so many traces and these are you know manually laid out it's very easy to make a mistake mistakes can be when you need to move some traces from one layer to another and you manually move them and then forget to adjust the widths or spacing for the new layer so how we're going to catch those mistakes and how we're going to make sure that we don't waste a you know precious time simulating um only to find that uh after the simulation is done there was a problem with the substrate stack up and i've got to throw away my results so what we're introducing to you today is scan z0 it's a quick check for trace impedance you kick it off from inside of si pro it's going to help you to quickly detect errors in the layout and and it's going to give you more information because it will tell you information about the individual sections of each trace and even give you skew information as well okay so you know in a nutshell why should you care well in just minutes you're going to be able to detect errors in the trace routing or stack up you can quickly find nets that are outliers in a group so comparing nets to each other and the last thing is is that we don't have time to em simulate everything so reduce risk don't leave any nets unverified at least check with uh with rapid scan first so now i'm going to share my screen this is a board in si pro and you can see what i've done is i've just filtered to look at the nets in the the memory uh channel so i'm selecting i'm going to choose all of the data nets so i've got 64 data nets right click rapid scan analyze transmission and what it's going to do is it's going to go and break uh break up each and every one of those traces into its constituent sections and that's going to report to us what the characteristic impedance of the longest section of the trace is so i'm just setting what what i determined to be the the desired impedance 34 ohms and you know 10 up and above and below is what i would class as being pass or fail and then here it's telling me now that all of these traces except for this one happen to be around 34 ohms this one of course i edit it on purpose in the layout to make sure that it's stuck out but if you select them it's going to tell you more information about that individual net so it says 33.9 ohms but that's for the longest section of the trace and down here on the bottom you can see that there's other sections of traces some that happen to be higher in impedance and then it's also represents the vias as well now what would happen if i selected multiple nets at the same time if i selected multiple nets what it's going to do is going to compute and compare the the we know the total length and it's going to compute the skew between them so that i know what i've designed for and i can compare and make sure that these things are actually length matched or not and then so that i can identify where something might be or try to uh find out um like to visualize um a trace that might be uh not meeting the requirement i can visualize it all just need to remove these guys and we'll take a top down view and zoom in and you can see that it's showing us here the green traces happen to be the ones that are passing the metric the blue happen to be traces that are outside of the metric okay so last thing you might ask about this would be can i can i do differential pairs as well yes absolutely you can and you might want to know about the vias hey why don't we specify what the impedance of the vias well that's a really good question the reason you don't see the impedance of the via is because this via's impedance depends upon the ground stitching vias as well as the you know the the anti-pad clearances around the via and so to get a good idea about how well our visas are performing what we really need to do is to make sure that we can um that we can use a tool like via designer this is the second part of the demo via designer is a tool that helps you to build a very very fast and very accurate uh model here um of uh a via it's a differential via these actually actually happen to be micro vias so two laser vias stuck on top of each other and then turned into an array and this is something that that's brand new in ads 2021 is the ability to now use via designer to create arrays of years so what you see here is um you set up the via by um going through this is for the the pad stack you can specify all of the different settings here you can add a variable if you add a variable it comes down into the table which you can then sweep for your micro viewers you get the ability to add them and uh even set things like a conical shape for the laser via you can do back drilling and you can have multiple feeds so for things like ddr vias you might want to come in and feed in at a center center of the via and come out at the center of a via meanwhile having a connection at the top and bottom all of that is possible and the newest thing is this ability to now create the same instance just replicate it in multiple locations and you get to adjust and pick the x and y parameters okay so then once i've done that what do i do once i've got a sweep you're going to press check to check the geometry it'll go through all the possible combinations that you're sweeping through make sure you don't have any issues you don't have any shorts and then you go and run press simulate and then you're going to get the simulation results here and so um simulation time is a is pretty reasonable um for a vr array like this we're using it's a 3d finite element method solution and it does an iterative refinement of the mesh and so it solves this problem to 80 gigahertz in 10 minutes and then if i want to compare two different uh two different simulations that i've run i can quickly press select them both and press s parameters and it's going to show the results overlaid and of course because these are differential vias we really want to see the differential to differential and differential to common mode and all of this is built inside a via designer so that's the process you analyze the vias you make sure that uh the via response is how you expect it and then we're going to export it to um to a schematic and you drop it on your schematic it's going to look like this and then you connect up your tx and rx and uh and so we've got r1 transmitter and receiver and then these are the the crosstalk sources either side and what would be the result of that simulation so for that i'm going to pass back into into the slides okay right so this is the results then of the simulation so on the left-hand side you've got um one vr array on the right-hand side another we instinctively uh believe that the one on the right probably is better for crosstalk but we don't tend to have us that much space on a board so how much worse is the one on the left we're doing a system simulation with this parametric model enables us to quantify it so you can see that um that the the one on the right is better by 13 millivolts in eye height 3.2 picoseconds in eye width um and maybe that is uh is is okay that we can live with a reduction in 13 millivolts and and the eye width being being less as well okay so last things is just to summarize now yes we can do conical vias for the lasers yes we can do vr arrays we can do diving boards for added impedance control and we also can support teardrop pads so summary via designer benefits you it's very easy to set up a parametric model very easy to generate that model you export it to the schematic and now that one model is available with all of the individual s parameters stored underneath that one model it's also included in every single pathway of hsd bundle so if you have ads already you should have access to it and we've got a success story that you can go and take a look at that was the winner of uh designcon best paper award okay thank you very much pass back to you tim thank you for the great demo and mr slater i'll talk to you later now we're going to move on to the next piece that is about power integrity and with that i will bring up heidi my favorite hb person now again there's a minute demo challenge format i will start a timer as you start speaking and it's gonna you have to show the audience a why you should care demo and then the takeaways without further ado heidi please take it away thank you tim here we go advancing the power integrity workflow with pathwave ads 2021 with pi pro why do we want to simulate well here's a great example this is a xilinx fpga characterization board that we can bring into a simulator and run an em simulation on but more to the point we can take that em model and run a full pi ecosystem simulation that actually shows down here in the left that the worst case power rail noise ripple and also not just voltage ripple also current ripple so the blue is current the yellow is voltage if we think we're running worst case at the very high 200 megahertz mission load serdes switching speed um and pulling 13 and a half amps it's not the worst case in simulation we can actually show and we can go find that the worst case noise is at 30 megahertz with only two and a half amps of uh dynamic current at the load and here you can clearly see that the voltage and current ripple is much larger at this lower frequency with lower current so the key takeaway here is that you really want to look at dynamic current and voltage at the fpgas pins to determine the worst case power rail noise so let's go see how we can do this type of analysis we're going to show you a quick in less than eight minutes tim how to do a basic power integrity workflow we're going to start with a dc-ir drop make sure the board imported correctly and that we're getting the voltage from the vrm to the sink and we can look at the margins uh power rail margins and then we're going to just copy that analysis to an ac analysis and generate our em model look at target impedances and then we can export that model em model with all of the capacitors already attached to a simple schematic symbol drop it into pi ecosystem simulation and get our time domain and frequency domain results so let's go ahead and jump right to that demonstration and i'm going to share my screen if it'll let me share my screen and i will go ahead and it says i'm sharing so tim just give me a thumbs up or actually a verbal thumbs up when you can see my screen um well verbal thumbs up pending okay pending here we are yes confirm okay confirmed here we go this is ads main window that i've just opened up and this is the workspace with the uh fpga characterization board and i'm going to open up this hierarchical schematic that lets me organize my workflow so i import the board as my first step and we're going to go ahead and we can see that we've imported that board and then there's an sipi we can just go ahead and open up fi pro pi pro which i've done for us the board comes in it's a 3d em simulator and you can expand the board see what it looks like there but what we really want to do is go ahead and get our analysis set up and it's really simple when you bring in a board for simulation it brings in the nets it brings in the components and i can just start an analysis create a new one you can see here i have analysis one you can actually just click on the components in the graphical view here right click and say create vrm for analysis and if i do that it says which analysis it helps automate this whole uh setup and i can select the power rail i want to look at and if i do that select that it will automatically add that to my analysis and it will connect all of the power rail and ground pins in the uh from that component and i'm set up with that port and i can also adjust the properties the voltage i can also look at non-symmetric tolerances here asymmetrical tolerances for calculating my design power rail voltage margins so let's go ahead um i did the same thing for the sync i added that and one little trick here if i click on the switch power rail and the vcc power rail and look at the instances connected to both of those i can find the inductor that connects my vrm chip to the power rail and i can add that component to my analysis and then simply running that analysis it actually runs in about 10 seconds and i can go ahead and open up the overview and you can see once i open up the overview i will get my power tree that lets me verify that i'm getting my eight eight and a half or 0.8 volts to my sink and i can also open up a tabular analysis here that shows my upper and lower millivolts of margin for the power rail voltage getting to the sink now the next thing that's very uh makes simplifies the setup is i can take that dc analysis that worked and i have the voltage getting to the sync and i can simply copy to a duplicate and that's what i did here with the vccint and then my vrm setup my sync setup comes over i can uh add my capacitor components just by finding all the components connected to the power rail and what you'll notice is those models actually come in as a library cell it's already defined as a model on the ads schematic side and it automatically pulls that model in so i don't have to sit here and set up all of those component models when i run this simulation now this is a full 3d em simulation so it does take me about 20 minutes to run this whole simulation and um and actually and then i can look at the current densities and what's interesting here is if i look at the current where the current is coming from at low uh frequency 100 kilohertz a lot of it is coming from my vrm and i can click on my vrm here and show you where that's located um and it's it's uh i have to zoom out a little bit my vrm is bringing the voltage over from the bottom right here but if i go up to one megahertz you can see that the voltage starts to be delivered from the decoupling capacitors and those are larger cap up here at the top but also uh very interesting is if i go and look at the impedance i can actually because this is an fem solution i can turn off all of those capacitors and the impedance plot will automatically update very fast you saw that with the capacitors uh turned on and the capacitors turned off with all of the capacitors removed i am now looking at the capacitance of my power and ground plane and i can actually uh read out on the bottom here how much capacitance my power and ground planes have now let's go back to the ads schematic or actually our our pathwave power integrity workflow here and i'm not going to go into it today but you can go into ads and set up the models for all of those components and verify the both the the measured and simulated models and get the correct ones but here you can see that we've exported straight from pi pro you can export the full em model of that printed circuit board with all of the connections to the capacitor models and it's not just one model that it can connect it can connect multiple models and let you switch between those so this is a very powerful schematic model of our printed circuit board with all of the decoupling capacitors and that is simply added to us our full pi ecosystem simulation so here is our em model of the printed circuit board and we've connected up a simple rl model and we've connected up the package die model and we're going to on the right here create a dynamic uh excitation load at the die and then we can measure the impedance with uh at different locations or the current with probes and if we run our simulation here we're going to run an s-parameter simulation and a transient simulation and what's very interesting is if we look at the results from the s-parameter simulation at impedance versus frequency we notice that if we tried to measure at the bottom of the fpga through a single via or a single you know going from a capacitor through a single via to the power and ground layer we have too much inductance we can't really see what the die sees but in simulation we can actually see the impedance that the dye sees all the way out to uh into the hundreds of megahertz but what's interesting is there is a peak impedance caused by the inductance of the print circuit board pdn with the package capacitance that's at 30 megahertz that's where we're going to expect to see some noise and sure enough if we excite our dynamic load if we force uh to have a forcing function at 30 megahertz then we will get the results that i'll show you here we're going to go back to the presentation so we're going to see the results so with that simple very simple power integrity ecosystem simulation we were able to change the the dynamic load at the die and show that at 30 megahertz at that impedance peak we get the worst case power rail ripple these are on the both on the same scale for voltage and at 200 megahertz it's the ripple is much smaller even though the dynamic load at the die is about five or six times larger so power integrity is not intuitive you need simulation so within summary of the demo we showed you how quickly to you start your power integrity workflow with a dc-ir drop you then copy to an ac analysis and get your em model and that can then be exported and directly used in a full pi ecosystem simulation if you want to go further and increase the fidelity pi pro has dc electro thermal we have ac decap optimization to select and optimize the the capacitors and loading and we also have the ability to connect very high fidelity buck regulator state space average models in the ads schematic and run very fast harmonic balance simulations to get both large signal and small signal performance and i also before we wrap up here i want to remind everybody that keysight workflow is not just simulation we have both simulation and measurement solutions including low impedance network analyzers measurements we have the real-time scopes and if you and also current analyzers for measuring those dynamic currents and we're not the only ones saying that ads pathwave ads with pi pro is the best solution for power integrity simulations here is an expert in the industry steve sandler of picotest he's a keysight certified expert for our eda software and he has done five how-to videos to ramp you up fast on how to design for power integrity takes less than an hour to watch all of them and they all come with their own downloadable ads workspace and steve sandler is often heard saying pathwave ads is the only tool that can simulate the end-to-end power integrity ecosystem so with that let's take the guesswork out of power and delivery test drive pathwave ads with pi pro today your best power integrity design will be your next one back to you tim and we're going to start another demo right away again this eight minute demo again i'm gonna remind the remind the the contestants here and vandana please take it away on your electrical optical electrical solution demo hey everybody starting now great okay so vandana here today i'm going to talk to you about the pathwave ads electrical optical electrical solution so first let's cover the challenges behind why we created this solution so with data centers rapidly growing especially with the higher demand with everybody working from home and different applications such as video streaming and 5g data centers are now migrating to higher speeds such as 100g to 400g and with this higher demand optical fiber interconnects have now become the preferable choice for data centers to support this increasing speed and the need for power reduction so let's go ahead and talk about the design and simulation challenges as a system architect or an electrical engineer have you been in a place where you need to analyze the entire link and to end passing through different domains let's call this challenge number 1 challenge number 2 what about simulating the design and the complete link within a given bit error rate target challenge number 3 are you looking to characterize transceiver performance with a modified set of parameters such as fiber length or laser power let me show you how these challenges are answered with our pathwave e-o-e solution so now i'll go ahead and share my screen okay great so here we'll open up the schematic this is a typical 400g base fr4 transceiver with the full end to end link so how does the simulation work pathwave ads is the platform that drives this e-o-e analysis where the electrical and optical parameters are open to manipulate by the design engineers so the simulations dynamic which means that vpi design suite is called to process these signals from ads and returns it back in an interactive way so the electrical system here is all represented by ads and the optical right here in the middle is represented by vpi photonics on the left you can see the tx ami which generates the pam4 signal and on the other end the receiver side which is where ctle is applied so we've got three eye probes here one two and three which is where i'm taking the signals and measuring the eye data so let's check out the results of this simulation here three different eye diagrams which is where we have the three probes at the receiver output after the optical channel and at the receiver output after ctle equalization so this shows here that challenge number one has been addressed now let's address challenge two simulating the complete link for a target bit error rate with the same example the results show here the eye diagram at different number of bits simulated as well as the timing and voltage bathtub with the bit error rate contour so if you want to send 1 million or 10 million bits within a reasonable simulation time you can get a more accurate plot i won't run the simulation today but i'll just show you the examples or the results here so as you can see as the number of bits increase you can see the eye will close due to random jitter and with an increased number of bits you'll be able to calculate the bit error rate in a more accurate way so with these results you can see that challenge 2 has been addressed you can simulate the design in the complete link within a given bit error rate target so now let's address challenge 3. we'll use the same schematic but look at the sweep version of the schematic so with this you'll be able to observe the performance changes due to the manipulation of various optical parameters so let me go ahead and click on the vpi optical link and real quick open this up in the background so we can see what's going on from the vpi design suite end okay go ahead and open and while that's happening in the background we'll go ahead and look at what's going on in the vpi optical link so here this is where you can enter in the design parameters that you can manipulate so you can enter in the optical parameters using the vpi optical link component in ads and here in the schematic as shown you can perform a sweep a parameter sweep now let's check on how it's coming along opening in vpi design suite which is where i'm going to show you how we can interact with the optical parameters from vpi design suite into ads okay here we go so we'll go ahead and edit parameters and here you can see the ads vpi optical link parameters so here you've got fiber length and laser power so this is how ads is picking up these parameters um so this is how ads reads in the information so the optical parameters are coming in from vpi into ads so now let's go ahead and take a look at the results from the simulation go ahead and switch to here and see we can go ahead and look at how laser power and fiber length impact your eye so you can go ahead and click on the toggle and use your left and right arrow keys to see how this impacts your eye and you can do the same here for fiber length so by performing this parametric analysis you can see that the laser power actually has a larger impact on the eye than the fiber length you can also view the eye height and width at a specified bit error rate and look at vsr pam 4 measurements so this shows that challenge three has been addressed so in addition to these three challenges being met you can also perform tdeq and advanced pam4 measurements let's take a look at this schematic here you can see the flex dca probe right here and this allows you to perform tdeq and jitter measurements using the flex dca software and now you can actually click on the flex dca probe and input the parameters directly into ads to set you up for these measurements so to conclude let me jump back to my slides keysight technologies has partnered with vpi photonics to create the industry first integrated workflow to allow system engineers and electrical engineers to analyze the entire end to end link you can simulate the entire link that contains the mixed domain channels observe performance variations with different parameters simulate the design within a given bit error rate target and additionally perform tdeq and advanced pam 4 measurements with the flex dca software and for more information we do have an e-o-e youtube video that will follow the the demo similar to what i covered today as well as an in-depth webinar to cover this in further detail and we'll have those links provided to you as well and that concludes my section thanks tim back to you all right all right all right now the final contestant mr heesoo you have eight minutes the clock is ticking right now is you take it away okay sounds good all right let me do my demo and uh this is all about data memory designs and we released a new product which is called memory designer last march which is a little bit over one year ago one of the main target area was ddr5 i'm not sure how many of you are actually doing the other ddr5 probably i say most of you know people are doing a ddr4 at this point in time however i know that yet everybody will be moving into the ddr5 very soon or later that's because uh you know czech recently announced the refiner version of the spec for ddr5 so there is no brainer uh it's no brainer uh you know thinking that everybody will be moving to the other ddr5 so the key about ddr5 what makes the ddr5 very different from ddr4 yeah speed grade is a lot higher almost doubled right but just using it you know just seeing a same channel being able to open the eye at higher data rate is very very difficult that's why ddr5 you know adapting a ami which is doing data equalization such as the dfv or ctle that's what a makes a big difference between ddr4 and ddr5 memory designer you know comes with the complete solution for ddr5 especially with the ibis ami and along with the other those equilibriums so i'd like to show you one example starting with a jitter tracking for the old technology like ddr3 or iv a lot of timing and analysis were done but moving into the ddr5 and more of their eye data and their mass management margins and that kind of stuff are more a standard in a measurement uh that's where how people need to be quite cautious about about the other jitter and this is the other and one of the example i want to demonstrate so memory designer basically used a very simple a concept to build up the design uh one with a you know a controller uh this we call a smart component that represents an entire controller with a multiple a wires and then in the in the middle other is pcb if you want to include a thin connector no problem you can you know include the other thin connector uh as a similarly smart component same for the other memory once you have the design you can just go and then run the simulations in order to save you my time for a discontest um i'm not going to simulate it although it takes only a 40 second let me just open up the other in a window and show you the result here is the sorry i clicked the wrong one here's the church juror tracking if you look at this is where we're measuring eye data right after the channel right so without having any of jitter it looks great but then when you are adding the editor running at the other 48 megahertz and 50 feet per second you can see the other high data is completely closed so how you open this data by applying data you know dfe uh for example to the receiver uh with a node jitter case yeah you know it opens up the other eye data with a 4dfp because the eye itself is very clean but when you are putting there is you know very much close the eye data into the receiver uh the equalization must be kicked in and it open up the eye and as you can see even within 48 megahertz and 50 picosecond jitter that were added both of a dq and dq strobe eye data can be still you know quite well opened this is how a uh you know equalization works especially in working with you know finding out the best optimum a dfe clocking by having the other two inputs coming to the ibis-ami model which is you know data and data strobe right so second interesting a kind of challenge is something about the other unmatched io in ddr4 case dq and dq strobe must be a more likely same length but moving to a ddr5 areas it doesn't need to be so that means you have a kind of you know freedom to have different length of the tq and dq's strobe which created a kind of skew issues so the question is can you really open up the eye with the skew coming in between the dq and dq strobe the answer is yes i'm going to open up the other the the simple a same design but in this case i'm applying the dq and dq strobe with a different uh you know delay applied that makes it a jitter correlation less correlated between dq and dq strobe but by having the two inputs ibis-ami model which is based on the other gateway 2 you'll be still able to open up the eye which is the result i'm going to show you uh right here so the top case was the one we uh you know uh ran through over the jitter uh tracking case yeah still we are able to open up the eye uh no problem but let's make the other dq strobe a 50 pico second uh additional delay added uh still we are able to open up the eye no problem because we have two inputs and where we are tracking the at all the inner jitters as well as you know phase interpolation is applied to make the other you know optimum dfe working uh along with the other those you know skews coming between dq and dq strobe if you look at the other bottom one this is a quite exaggerated case where actually dq strobe is five ui which is around the one data you know is quite open right so these are all the things uh what we have done for ddr5 then now you may ask the other question uh this sounds good but i don't have any of uh you know ibis-ami motor that i can use for my ddr5 applications i have to tell you don't worry about it memory designer comes with a memory interface ami model builder so if i just go and click this button it brings up a this window where i can specify i like to build up a new uh ami model something like it right and then go to the next uh or give me what kind of choices you know you have for the devices let me choose the rx controller then it shows up the old tab which is related to the ddr5 ami model such as delay a vrep calibration even adding the ctle multiple poles and going to enable the dfe if i enable the dfe then i can see all the tab values i can enter and i can go with the other clocking that allows uh you know me to generate the model based on the gateway or gateway 2. it doesn't matter but after you've
finished this up you just go and then say uh uh just go in the build the model then you just build the model then it generated a dll and ami uh files that can you that can be used in your design right away so although you know there might be some challenges not being able to get to the ami model in memory designer case and no problem at all right last year a couple of things i'd like to show you uh moving on to the other more of the ddr4 cases a lot of people are wanting to simulate their corner cases or even you know simulating the the high performance based on the other different odt values we made this process really really simple and straightforward so if you look at uh this is the one of the typical a ddr4 design example that comes with the controller and motherboards then steam connector and dim board and memory right now we can easily create this dispatch assimilation which is switching through the different odt values and here's the results this result of a odt swipe shows eye data but by moving the other different a odt settings i can see eye data will be changing if i put the 120 ohm odt value i can see that eye got you know a lot smaller than the odt value of 40 or 48. so this is the typical a type of the task design engineers wanted to go the answer to that yeah no problem at all last thing uh just quickly going over uh we added a new capability called a design exploration this design exploration allows you to enter your own own a design specification such as i'd like to have the minimum size of eye height something and something and then you can run the batch assimilation and make sure every cases are passing through that specification and eventually we'll be generating excel spreadsheet so that every case you see that it pass or fail so by having this data you'll be able to see what certain cases are failing to the specification so that you can dive into the other you know that specific a configuration more detailed uh to fix uh the design issues right right uh that's all there are a lot more but due to the timing i will stop it here back to you tim all right thank you mr heesoo make sure you check out these slides in the resource resources center you have a bunch of compilations of the great things that's happening i just want to thank you all for uh presenting and thanks to the attendees for spending time with us whether you're live and on demand we are here to help you this is very clear we provide solutions to you so remember to fill out that survey and let us know how we did and again as we wrap up today's presentation remember that we will email you a link when the on-demand version is ready to view thanks again for attending our uh new technologies for si and pi simulation and pathwave ads 2021 brought to you by keysight technologies please visit visit us at www dot maybe that was too many w's keysight dot com forward slash fine forward slash events for a list of upcoming events stay well and be good thanks again everyone have a beer
2022-06-24