New Disruptive Microchip Technology Explained. ASML is out?
modern life runs on semiconductors and TSMC is arguably the most important fab in the world it makes around 90% of the world's most advanced chips now TSMC has announced a new technology that will take us beyond 1nm as a chip designer I can tell you this is a big deal for the entire industry so in this video I will break down the genius behind this new technology what is the next big thing in semiconductors what's going on with the TSMC stock price and why we will rely less on ASML lithography machines in the future when TSMC was starting out in 1987 their first chip was manufactured in 3 micrometers technology that's 3,000nm just think about it and recently they announced that they are ramping up the production of 1.6nm technology this means that over the last 40 years or so they managed to make their chips 99.99% smaller and the next big breakthrough is just around the corner and it involves new materials and a cutting-edge transistor architecture CFET but to truly grasp the beauty the genius behind this we must start with transistors first if we go back up until around 2012 the basis for all silicon chips was so-called Planar transistor and we love Planar transistor because this one is very easy to understand it's just like a tiny electronic switch which controls the flow of the current imagine a pipe with water flowing through it if you place a valve in the middle you can turn the water flow on and off in a similar way transistor controls the flow of electric current it has three main parts source where electric current starts drain where the current exits and gate which is used to control the transistor when you apply voltage to the gate it creates an electric field that either opens or blocks the path between the source and the drain so this Planar transistor remained the state-of-the-art technology for about 50 years but when we were approaching the 22nm process scaling its dimensions further were no longer possible what's interesting for a long time we were reducing the gate length but further reduction were causing the channel becoming too thin which resulted in electron tunneling from the source to the drain and that's bad imagine in the example of the pipe imagine you close the valve but the water is still leaking so basically we were not able to control the transistor anymore and as you will see today since then it has become all about the gate the first step in this evolution was to stretch the channel in a kind of Fin and wrap the gate on three sides of it this new architecture was called FinFET and this was a very elegant solution because the gate wrapped around the channel allowed for better control it which means it could be faster switched on and off quickly improving the speed of transistor and allowing us to pack more of them per silicon area these new transistors leaked less power when they were switched off means devices can run longer on a single charge in fact Intel was the first to manufacture FinFET devices which hit the market in 2012 at the 22nm process node and one year later TSMC also moved to FinFET devices in fact today almost all high performance electronics including Apple Silicon NVIDIA and AMD GPUs are manufactured in FinFET technology now we are coming to the most interesting part as of today the limits of FinFET architecture has already been reached and now the industry has to take yet another bold leap in transistor architecture now we are entering the truly 3D era of transistors and remember it's all about the gate if you think about it the only way to shrink the footprint further and get even better control of the gate is to control it from more sides here the genius is in turning the channel on its side stacking horizontal nano sheets instead of standing vertical Fins now instead of growing horizontally the nano sheets are multiplied vertically and this design allows the gate to fully wrap around the channel so a true gate-all-around structure eliminating leakage and improving electrostatic control and good news the first gate-all-around transistors are coming in N2 technology is already entering the mass production and first devices coming to iPhones now let's talk tools even though gate-all-around architecture was an evolutionary step from FinFET where TSMC was a decade old leader still many processes had to be readjusted and here the general trend is that from now on EUV lithography machines will be less on the critical path and other tools and noble materials will become more and more increasingly important EUV tools essentially create a controlled tiny explosion inside the machine and use the high energy emitted photons to print the finest features on the wafer and this process is beautiful it's often compared to tiny star explosions because there is a similar process behind it it involves extremely high temperature plasma generation similar to what happens in the Sun if you look at gate-all-around architecture the main challenge is to create the channels and wrap the gate around it especially when you can't directly see the underside of the nano sheets that's where atomic layer deposition and epitaxial growth become critical it's crucial here to precisely deposit gate dielectrics and metal gates around these intricate shapes and for these steps Applied Materials and ASM not ASML but ASM own the secret sauce what's more after the deposition we have to edge away the material in between the channels and here lateral etching tools from LAM research are critical and finally we need one more deposition step where the gate around the channels is formed and here again the tools from LAM research and ASM are critical so this is the elegant solution behind today's state-of-the-art gate-all-around transistor architecture which is mostly about going vertical and this will enable shrinking beyond 3nm what's interesting we had Planar transistor for 50 years and then we had FinFET as the state-of-the-art for a decade how long gate-all-around will last after roughly 30 years in the making probably five years or so just one of many examples where we see everything accelerating technological progress is accelerating as Ray Kurzweil said we won't experience 100 years of progress in the 21st century it will be more like 20,000 years of progress at today's rate i totally feel that do you we all know that AI can help us now to create things faster than ever and one of the most exciting shift is happening in the software development what if I tell you that I managed to create a custom made web app with just one click without a single line of code with Hostinger Horizons you can turn your idea into a fully functional web app using AI generated code no coding no complicated deployment no third-party hosting just couple of clicks and you're live here is how it works simply type your web app concept into the AI chat box and watch as the AI instantly generates the first version of your app and in case you need any changes you can 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lies in details in the new stacking approach instead of placing transistors side by side the new architecture consists of a vertically stacked PMOS transistor on the bottom and NMOS transistor on the top and this cuts transistor footprint by half and keep Moore's Law going and this new architecture is called CFET Complimentary FET Transistor other companies calling it differently but the idea is the same the next big thing in semiconductors is a vertical transistor the bottom layer contains a P-type gate-all-around transistor called PMOS when a negative voltage applied to the gate it creates a channel of holes allowing current flow and the top layer contains an N-type nano sheet transistor and here a positive gate voltage creates an electron channel enabling current flow both NMOS and PMOS nano sheets are surrounded by gate material forming a gate-all-around structure the sheets are typically very thin around few nanometers and narrow around 10 to 15 nanometers what's interesting one of the key persons responsible for the CFET development at TSMC is Szuya Liao she is a director of device architecture pioneering at TSMC and she joined TSMC in 2021 after 16 years working in Intel where she contributed to all the latest development from 65nm down to 4nm process now at TSMC she's pioneering new device architectures such as CFET while at the same time looking into the integration of novel materials which we will discuss in a moment her recent paper describes the first working CFET device and it's a pretty remarkable achievement recently at the latest International Device Manufacturing Conference TSMC presented the first working CFET and they managed to solve the interconnect challenge to interconnect the bottom and upper transistors and it seems that TSMC is leading CFET development and being ahead of the rest of Samsung Intel and even IMEC the main challenge with CFET is interconnect complexity you know interconnect those tiny fine metal lines that interconnect all the transistors and other electronic components on the chip usually it's a complex network complex metal network of up to 20 layers that enable data transfer and power distribution across a chip and in modern chips interconnects run mostly in horizontal layers across the chip now with CFET the connections must go vertically which again increases the resistance capacitors and add additional delays slowing the signals down and increasing power consumption adding complex vertical interconnects means more processing steps new alignment challenges and potential defects in wiring and it would probably require backside power delivery and potentially even backside signaling for the PMOS transistor not to mention extreme thermal challenges that are coming with this new architecture already now the high performance NVIDIA GPUs generate several hundreds of W per square cm of silicon and it's projected to reach 1 kilowatt per square cm of silicon now imagine what will happen when we pump 1 kilowatt of power into this tiny multi-layer transistor piece of silicon which is a part of a 3D package it's going to be hellishly hot so CFET approach to scaling is genius but it comes with a whole new set of manufacturing challenges more processing steps higher cost at the moment is expect to reach mass production in roughly 2030 and this will allow us to scale the transistors beyond the 1 nanometer node as you saw in the early days of the transistors innovations were primarily focused on geometry but now the focus is shifting now TSMC is pushing on the development of new materials mostly focusing on the 2D materials with the goal to use them in the channel of the transistor you remember early in the video we discussed the problem which arised when we tried to shrink the Planar transistor the gate of the Planar transistor further this is a limitation of silicon that's why researchers are now focused on other materials to push the performance further it turns out that 2D materials are more robust to the effects causing leakage and much easier to control in general TSMC is mostly focusing on TMD materials i will put them on the screen and these materials have the potential to enable atomic thin channel transistors but those are still mostly in the research phase and still quite far from commercial use and the main reason for that is the growing process of 2D materials currently they are grown on the sapphire wafers and then transferred to silicon wafers and this is not scalable for mass production to enable the mass production we have to learn how to grow them directly on silicon wafers in fact I have about three to four episodes on this channel about semiconductor material innovations covering 2D materials indium selenide graphene and other materials so subscribe to the channel now so you can enjoy them later on another big shift worth mentioning in this episode is towards material innovations and if we look at the N2 process node and also all the innovations we just discussed we see that the trend is that the focus is shifting from lithography tools towards other processes and mostly material innovations to be clear EUV lithography tools will be still important what I mean is they will be less on a critical path towards future transistor scaling over the past few years we talked a lot about EUV lithography machines and that's because they were crucial for transistor scaling and as transistors were becoming smaller and smaller the interconnect which connect all these transistors into logic gates all of this had to also scale down in fact transistor scaling was always outpassing the interconnect scaling let's say at 7nm down to 3nm EUV machines were the most critical tool for scaling because older DUV machines Deep Ultraviolet Lithography machines which use longer wavelength light compared to EUV machines were not enough to pattern the finest metal lines for the interconnect layers but looking at the latest process nodes like N2 from TSMC its role is decreasing it's decreasing because we are shifting to CFET architecture which has its own challenges and because we are shifting to backside power delivery which is actually removing the congestion of interconnect on the top of the wafer this shift to backside power delivery is a big change for the entire industry because till now all the metal so signaling and power layers all were placed on the top of the wafer now the idea of the backside power delivery is to offload the power to the bottom of the wafer so those metal lines which are thicker and wider which are used to deliver power they will have to go on the other side which will free up the space on the top of the wafer and this means with backside power delivery we can reduce the number of fine-pitch layers on the top of the wafer means fewer exposure steps fewer EUV masks and lower cost and this is a big advantage for going beyond 3nm while EUV tools from ASML are less on the critical path TSMC remains the most critical fab that the entire world depends on so then what's going on with TSMC stock why it has gone about 15% down over the last few months one of the contributing factors is concerns over potential US tariffs on computer chips that could reach as high as 100% well I think it's a part of Trump's strategy to encourage TSMC to build fabs in the US and this is driving the stock down which means shopping time because despite all these concerns they show strong revenue growth about 43% year to year which shows strong robust demand in silicon chips now consider the high costs required to building the cutting edge fabs and also the costs of constantly upgrading equipment to staying on the leading nodes no surprise that more and more fabs are dropping out from this race you know in 2007 we had 12 fabs manufacturing chips at 45 nanometers and now we have come down to just two fabs fabricating silicon in 3 nanometers and with Samsung and Intel recently struggling with yields it's really just TSMC leading the charge so the role of this company in the modern economy is undeniable and a few days ago TSMC announced their plans to invest another $100 billion dollars to expand its semiconductor manufacturing in the US for once billions are coming in instead of other way around that's a change and this investment will be used to build three additional fabs in advanced nodes two packaging facilities and we know that packaging is so important for the advanced GPUs and in general a part of the success of keeping the Moore's Law going and they will also build one R&D lab as you may know they're already building two advanced chip plants in Arizona with the first set to begin production already this year and the second planned for 2027 and this is a huge fap it's hard to imagine how huge it is it's around 1100x in size which is roughly equivalent to 650 football fields and this making this manufacturing facility one of the largest semiconductor production sites in the world anyway I think the costs of TSMC chips will go up whether as a results of high tariffs or higher manufacturing costs in the US let me know what you're thinking in the comments as Stephen Hawking said we are standing on the threshold of a brave new world what we do with our discoveries will shape the future of humanity clearly the next decade in technology will be defined by AI and high performance computing which are demanding exponentially more computing power and the key bottleneck is energy we are currently hitting the limits of what our power grids can deliver and what our cooling systems can handle without power efficient transistor technologies our data centers will hit the power ceiling and clearly we need new materials and a breakthrough or two in semiconductor technology to keep up with AI power demands i think it's rather going to be a complex solution which means noble materials new architecture of transistors integrated cooling technology including also backside power delivery chiplet approach with photonic interconnect and advanced packaging it all has to come together let me know what you think in the comments now check out our sponsors in the description below to support the channel and watch this video where I explain the backside power delivery how it works and the secret plan of Intel or this video where I explain the new photonic chip which is on the way to data centers right now and connect with me on LinkedIn all the links are below thank you for watching love you guys ciao
2025-03-21 12:41
