Implementing Infineon's CoolGaN: Key Essentials and Best Practices -- Infineon and Mouser

[Music] if you could imagine the best switch ever made the world's ideal switch what would it include zero on Resistance instant on and off would it be made of Gan well yes it would and no the ideal switch isn't reality yet hi I'm ailia do and host of chalk talk in this episode of chalk talk Z Rani from infini and I explore the fundamentals and characteristics of wide band Gap materials we also investigate why the higher band Gap and higher electric field withstanding capability of Gan brings us closer to that ideal switching technology and the unique design challenges one must pay attention to when driving Gan devices and before we get started don't forget to click that link there you can find even more information about this topic from infinion hi Zoe thank you so much for joining me thank you be with you so we're talking all about Gan today but before we get started what all will we be covering today so today I'd like to cover Gallum nitrite hemp I electron Mobility transistor which is a wide band Gap switch and I like to begin our discussion by covering its fundamentals ways we can drive it best methods to lay it the devices on our board and outline some performance expectations of Gan versus existing silic and finally I like to also highlight some updates in terms of latest development using Gallum nitrite technology so can you set the stage for us what are the characteristics of a wideband gap material to best understand the advantage of Gan as a wi band Gap device it is useful to draw a comparison of highlighted semiconductor characteristics on this slide namely the band Gap breakdown field electron Mobility thermal conductivity and electron drift velocity and so I'll go through each one so we can better understand each metric so we start with the band Gap the band Gap is an amount of energy required to pull electrons from the veilance band into the conduction band and the higher the band Gap the higher the electric field with standing capability of the device in fact actually the higher the capability of the semiconductor even at higher temperature the breakdown field or also the critical field determines the minimum amount of material before arcing can occur across the device and the higher the breakdown field the smaller the device may be electron Mobility is a metric of how easy electrons can move within a material obviously the higher the electron Mobility the less the resistance the moving electrons will experience within the material and the thermal conductivity is intuitive it is the ability of material to allow for heat transfer within the material and the higher the thermal conductivity the easier heat can travel through the material and finally the electron drift velocity it is the the average velocity an electron can reach when an electric field is applied and the higher it is the faster and easier electrons can move within the material and so as we can see on this chart shown and different colors silicon in Gray silicon carbide in green and Gan in purple we can see that Gan exceeds the rest of the Technologies by far especially when it comes to band Gap and breakdown field which makes it a great switch a wide band Gap switch what are the consequences of higher electric field withstanding capability for a wbg device higher band Gap and higher electric field with standing capabilities enable us to get yet another step closer toward that ideal switch which has zero on Resistance and can turn on or off instantaneously and we'll take advantage of this very simple and yet useful schematic to highlight the Gan advantage in this diagram a 650 volt potential is applied across a silicon device housed in the blue box on the left and across a gan device housed in the green box on the right the blue box is intentionally drawn larger as the Silicon semiconductor requires a much larger Mass to support the same electric field on the other hand since the Gan has a higher band Gap energy as well as higher electric field with standing capability as discussed previously to support the same electric field it requires much less mass and this has profound advantages that is electrons now can travel through a shorter distance which means less conduction losses and moreover since we have a smaller die and overall capacitance associated with a small D would also be smaller and it will allow it to have faster Transitions and therefore lower switching losses and at the system level what this means is that now we can switch at faster rate we can have less conduction losses so the system can enable higher power density and potentially even lower cost Z inside that green box you showed a gan device so how is the structure of a gan device different from a silicon one for that let's take a look at this more detailed cross-section of again at first glance it is evident that unlike a vertical silicon device which was shown in the previous slide again hemp is a lateral device that is current flows horizontally from drain to Source the next immediate difference factor is the heterogeneous structure of the Gan hemp as Gan devic is built on Silicon as the substrate and interestingly it only takes about 5 micrometer to grow the Gan device on top of the 200 micrometer of a silicon substrate and the choice of silicon as a substrate has been a critical factor in commercialization of Gan since silicon is cost effective and equally important existing silicon favs can be used to manufacture Gan without additional investment in new equipment next there is a transition layer in between Gan and silicon substrate to account for the differences in thermal coefficient of expansion as well as Crystal mismatch between the silicon and the Gan but the real magic happens when aluminum gallium nitride Alan is deposited on top of the Gan layer due to Crystal strain in nanometer distances and these are very small distances and pizo electric characteristics of Gan a two-dimensional electron gas forms between the two layers so that when an electric field is applied drain to Source current flows within the device however since in Power Electronics applications normally off device is desired a pan either in the form of an omeg PN Junction or a shot key is added to locally reduce the crystal strain and the posl effect and pinch off the channel this allows the device to normally stay off and only turn on when a positive voltage is applied at the gate a second p Gan is added near the drain to mitigate trap charges which otherwise led to unresistant variations when devic is dynamically switched this issue is referred to as Dynamic rdson which is now resolved by this structure shown here and finally the drain gate and Source metalizations are added to form the three terminals of the device so this lays out how a cross-section of a gan would look like and here on this slide it's a very nice drawing of Gan D shown on the left where the source and drain buses are highlighted in green on the left and the right side of the die and the small gate pad which is shown at the very bottom and then the middle image shows the Dy how it is soldered on the back metal Tab and wire bonds are attached to the drain padal on the top and the two wire bonds which are used to connect to the gate and the cman source connection and finally as shown on the very right the device is completed by epoxy mold injection as shown here it is important to note that unlike the majority of silicon devices the large back metal substrate is connected to the source terminal as opposed to the drain what would again hemp look like on a schematic level so as highlighted there are two main flavors of emote Gan there is the omeg Gan as shown on the left and the Shi Gan P Gan on the right the two diagrams highlight the parasitic structure of each device and indeed they are very similar so let's take a look at the omeg Gan pan first so all the components inside the dotted box are internal to the Gan hi the inductor external to each terminal that is the brain gate source and the celvin source are parasitic inductances associated with the immediate circuit board traces around the device at the heart of the diagram is the diamond shaped current source which highlights the two dimensional electron gas we mentioned in the previous slide between the drain and the source and the two resistors in serus one on the top and the other on the bottom signify the on resistance of the channel and given the physical proximity of the gate to the source the bottom resistors is a smaller portion of the overall on Resistance and then very similarly to Silicon devices and the CGS cgd and CDs which are the parasitic uh gate to Source gate to drain and drain to Source respectively represent the parasitic capacitances of the device and then the immediate resistor at the gate terminal is the internal gate bus resistance and the serious resistor and the diode from the gate to the source highlight the PN Gan or the panana structure and forward biasing of this diet allows the device to turn on and remain on and that is why it actually this structure also is getting the designation git or the gate injection transistor and finally the reverse stack Gan diodes are accounted to protect the gate from the negative spikes and turning over to the right side the shot key Pana structure is indeed very similar to the git except for the highlighted shot key connection at the gate but it does require a different applied vgs voltage which is actually making it more of a similar device to a silicon device okay so so B what should a designer expect in terms of driving a gan switch well will you utilize the schematic and the W firms uh in this slide to answer this question the schematic shown on the left shows the gate driver inside the smaller box on the left which connects to the Gan git switch which is also shown inside the dotted box through a simple network of passive elements to best address this question it is helpful to examine the vgs versus qg behavior of the Gan device which is shown by the turn on waveform in the middle of this slide with x-axis being the gate charge and the y- axis being the vgs itself throughout this segment it is helpful to keep in mind the structure of the Gan switch highlighted in the dashbox by the way given it Lower Gate threshold vth typically a negative voltage is applied when the device is off so the turnon process begins from the applied negative vgs and as vgs Rises the applied Source charges the CGS capacitor the gate to Source capacitance that is and at the the vth the devic starts to conduct current drain to source and then at the qgs point the CGS capacitor is charged and the device starts charging the gate to drain or the Miller capacitance and hence the designation on the Y AIS of V Miller and finally vgs is clamped by the internal PN diode from the gate to source so immediately looking at the gate current graph on the very right the first Peak that we see there is the one that shows the amount of charge that is carried by the gate driver to Source the entire qg total and this happens when the S1 inside the gate driver closes and the current flows through the r on and the uh cc to provide this initial P of current into the gate and then in order to keep the device on there's a small amount of current that continues to be sourced and injected into the gate through the RSS resistor and finally at the turnoff the gate driver turns S1 off and turns S2 to send current from the gate through the CC R off and the diode d off this process will repeat itself in reverse and so it's worthwhile to note that the Gate of the standard silicon device as well as a shock key gate Gan will have a similar vgs to qg and IG versus time waveform minus this is steady state current phase that is highlighted on the right for the git device would the schematic for driving shock key pan be different the short answer is yes and the differences are very subtle to extend where a unified layout with component populated options can be used for driving both shocky gate as well as the git G on this slide for example we have uh carried the git Gate Drive circuit from the previous slide on the right side and the Gate Drive circuit for a shocky gate is shown on the left since the steady state current is not needed in the case of the Shi gate the RSS resistor is shown in Gray however two backtack zeners are added to protect the Gate of the shoty pan device from excessive positive and negative voltages and contrary in the case of the git these zeners are shown in Gray and would not be needed because the PN gate structure itself actually clamps the voltage and there is exist the series clamping diodes as shown in the previous slide to clamp the voltage in the negative Direction and so at infinion we call this circuit Arrangement which can be used for both the shot key gate as well as the git gate the easy Drive circuit which allows the use of the same PCB layout to drive both shy gate as well as the git G so are there any other unique design challenges that we should pay attention to wind driving Gan yes indeed I would say the undesired turn on at first pulse might be the most important to cover in our a lot of time to best understand the issue we will review a typical half Bridge Arrangement shown on the left side and Its Behavior through the waveform shown on the right as you might know this half Bridge is a common building block for many power converters or inverter topologies and there is a lot of information embedded in the in the waveforms shown here and uh we'll do our best to quickly review this Behavior as it helps to better understand the Dynamics involved so looking on the diagram on the left when the S2 at the time T1 pulls the Gate of the high side low and negative voltage is impressed at the Gate of the switch while capacitor CC retains its charge the switch node W from at the bottom initially jumps to slightly above the bus voltage v+ by uh initial negative voltage vni plus the V threshold of the high side Gan device this is to allow for reverse current to continue to flow after the a lot at that time when the lows side switch turns on at the time T2 the green switch node takes a hard transition leading to a brief undershoot now looking at the highight vgs top graph through the charge distribution of the cgd to the external capacitance CCC and the parasitic capacitor CGS the negative voltage shifts slightly from the initial negative voltage to the VN but if you pay a close attention here at this instant there's also a slight Spike at the Gate of the high side noted by the vgp which is as a result of a current injected into its gate impedance through the Miller capacitor cgd this Spike must be less than the V threshold of the highight switch otherwise it could lead to an undesired turn on leading to a momentary short from the bus voltage v+ to the ground throughout the time where the high side remains off the negative gate voltage decays as shown Again by the top graph and the rate of Decay is determined by the RC time constant of the RSS time to CSS at the time T3 when low side turns off the switch node shoots up incurring an overshoot determined by the load current and the loop inductance and the negative load current leads to a transient undershoot at the high side gate as well and finally at the time T4 top side gate is turned back on now imagine due to a circuit operation such as an initial turn turn on or perhaps in Burst Mode operation for example the bottom side gate turn on was es skewed as shown by the waveforms in blue that is when we turn on the low side gate when the top side negative gate voltage has decayed to near zero the resulting a spike due to Miller effect which we just covered earlier could lead to the undesired turn on in this case as well leading to a shoot through condition which could manifest itself as in increased uh switching power dissipation uh for the system or in worst case it could actually lead to catastrophic failure and in fact in this Slide the waveforms on the top left again highlight the decaying negative vgs which makes the device susceptible to this undesired turn on and this is shown in the graphs a and the waveforms B and C show idealized conditions which indicate not only an immediate negative voltage to mask the spirus event but also an available negative EGS after required a lapse of time the diagram on the right shows a universal gate configuration for git and shke gate transistor which utilizes a bipolar power supply for the Gate Drive typically A Plus 8vt or a 6vt for positive turn on and a negative3 volt for turn turn office utilized in this manner whenever a gate is pulled low it will always remain at the minus 3 volt allowing for ample Headroom for a reliable turnoff State despite possible spikes due to the Miller effect okay so it sounds like parasitic elements within a circuit can alter Its Behavior significantly so why is this and is there a way to eliminate or educe parasitic elements that is very correct indeed uh parasitic elements especially inductive elements to a more extent then capacitive can lead to undesired circuit Behavior to best explain the reason and offer Solutions let's formulate a statement of problem and to do so let's quickly examine the various parasitic structures present in a typical battery operated three-phase inverter shown here as you can see there are parasitic inductances in series with the source in series with the battery disconnect switch in series with the shunt resistor at the bottom and of course embedded in the structure of each half since the highest speed transients occur within each half Bridge let's take a one half bridge in this case the green one as an example at the PCB level such a half bridge is constructed using either through hole or surface mount devices as shown here given its unique physical layout each half bridge design will end up with a certain cumulative Loop inductance which is a summation of PCB Trac inductances as well as parasitic inductances internal to each device so considering a standard inductor equation which stems from the fairday law the equation being V equals L * DT a quick calculations leads to understanding the significance of the parasitic Loop inductance especially when it comes to fast switching devices like Gan so assuming a hard switching half Bridge constructed using through hole devices with an overall Loop inductance of about 10 nano Henry and a current rate of change of about 10 amp per nanc we arrive at 100 volt overshoot which for a system that operates from a 400 Volt Bus this Con stitute about 25% overshoot and so the significant of this overshoot for a system is that it could actually either compromise the longevity of semiconductors used in the system or in worst case sometimes it could lead to catastrophic failures and this forces the designers to actually slow down the switching of the semiconductor which works against then the efficiency of the system and it will increase the losses okay so is there a better method to mitigate the overshoot due to Loop inductance yes indeed there is and it would help if we examine some of the fundamental concepts associated with inductance particularly the loop area and loop inductance so there are two Loops comprised of a discrete inductors shown here one closely mimics a circle and the one on the right looks like more like a fork shaped strip line in the circle shape there is little too no Mutual inductance as such the total inductance is the sum of individual elements themselves on the contrary with a fork shaped loop on the right due to uh magnetic flux coupling between the opposite elements on each side of the uh Fork shaped Loop there is a higher Mutual inductance as shown by the equation at the bottom and rightfully it subtracts from the total inductance this leads to a much lower overall inductance in the loop this concept can be used to reduce parasitic Loop inductance in a power converter half brdge as well how does this translate in terms of physically laying out the Gan device packages on the board to put that in perspective let's take a look at a simple half Bridge Arrangement both in the form of a schematic as well as a physical layout shown here on the ref left side of this slide so examining a best case traditional method of constructing a fundamental half Bridge block uh using these through hole 2247 devices we can place the high frequency decoupling capacitor C1 and C2 for example on the blue paths which extend to the q1 through the yellow polygons and in turn the q1 source you can see is connected to the drain of the Q2 on the right side through the turquoise color inner layer and eventually to the source of the Q2 which is then connected to the ground plane which completes a circuit by returning back to the C1 and C2 on the top layer and a typical power Loop inductance with such layout could be in around 15 Nano Henry and as noted earlier with fast switching devices this could result to an overshoot of about you know 100 to 120 volt and now instead of through hole devices if we construct this half let's say using surface mount devices and optimized layout where the discrete parasitic elements could have an opportunity to mutually couple provides an opportunity to reduce the overall Loop inductance here is a cross-sectional view of a half rdge realized using top side cooled SMD devices where power flows from the top right through the component components and top layer traces and returns back to the decoupling capacitors through the immediate in layer layer of the PCB this Arrangement allows for the magnetic flux coupling between the inductor elements on the top layer and the bottom layer resulting in higher Mutual inductance which in turn leads to lower loop inductances here are two examples using bottom cooled to leadless package and another using the top TT package while in both cases the loop inductance is considerably reduced for example in the case of the to leadless is only 6 Nano Henry and in the case of the TLT 5 nanry in the case of the bottom side TL package the return path is is still not fully coupled with the top inductive elements since space needed to be allocated for the thermal vas to take the heat away from the devices through the board however in the case of the top side cool devices as shown in the bottom as well as previously discussed in the top image there is a full utilization of mutual inductance coupling which naturally leads to lowest overall Loop inductance okay so considering the availability of silicon Gan and silicon carbide devices on the market today how do you decide which one is the best fit for a specific application the best method is to compare like device characteristics from each technology this chart shown on this slide outlines characteristics of similar rdson devices at 600 or 650 volt from each technology that is silicon silicon carbide and Gan through the various figure of merits that is RDS on times qss RS on times qrr and so on on these figure of merits provide a normalized mean to draw practical comparison of various characteristics of these devices the lower the figure of Merit of course the better the performance of the device here for example we are comparing around 50 mli ohm devices as noted on the third column the rdsi might vary but these are the closest match devices from different Technologies and the kulma 7 C7 and CF7 are silicon super Junctions in the last two rows are the cool Gan and cool sick which are the Gan and silicon carbide devices respectively and so let's examine these various figure of merits to better understand the advantage of one technology versus the other so looking at the rdson times qss for example this characteristics allows a Tim related assessment of how fast output capacitance of the device can be commutated as seen in the corresponding column both Gan and silicon carbet are almost an order magnitude less than silicon coolas devices with this characteristics White Band gab devices especially Gan enable the next higher level of switching frequency in resonant converters and allowing for a higher power density next looking at Ron times qrr which signifies the ruggedness of the device in hard commutation topologies such as continuous conduction mode totem pole power factor correction or even in resonant converters such as LLC where special operating points such as startups or fault events might lead to hard commutations so since Gan has no minority carriers to be cleared and therefore zero recovery charge it provides the ultimate performance in this category on the other hand looking at at the RDS on times Usos which is a critical figure of Mer especially for single-ended topologies such as classic PFC or flyback converters and it signifies the dissipated energy stored in the output capacitance of relevant devices and so while the G Advantage is not as profound compared to the other two figure of Merit we just reviewed it is still outperforms the Silicon as well as as the silicon carbide finally looking at the figure of Merit on the very right RDS on times qg so qg is the amount of charge Source or sunk at each switching cycle and the lower it is the lower driving losses which are significant of total power losses especially at higher switching frequencies and at light load conditions so uh overall it is clear that the Gan across all figure of merits outperforms all other semiconductor Technologies and the return could be even maximized when it is used in most suitable topologies as the one that were noted on this slide is there a practical limit in maximum allowable switching frequency using Gan devices indeed there is and designers must conduct early assessment in this regard for best results that is a acceptable power density and yet manageable thermals the par front analysis example for this 3 kilowatt Telecom converter shown on this slide puts this best in perspective let's begin first uh as a reminder to our audience of what par of front is which is basically a set of parido efficient Solutions generated by a multi-objective optimization process that is for each set of assumed inputs and settings best performance is achieved so as noted earlier on the right is a peri of front analysis for a 3 kwatt uh Telecom power supply this graph on the y- AIS designates efficiency right away maybe power loss then on the x-axis is the power density or another way to look into the x-axis is the switching frequency so the more you are on the right the higher the switching frequency so the result for the Gan is shown in a gray color Paro front and the par of front for the Silicon is shown in black and this analysis includes all power electronic components auxiliary Electronics PCB parasitics and even a 20% additional volume being added uh to account for nonideal placement of components so for example in this case if you take the 96.7% efficiency and draw a horizontal line to cross both the gray and the black we can see that the Gan technology enables almost 30% higher power density at this same efficiency Point another way to look into this as well is that at the same power density you can achieve a much higher efficiency with Gan as well so if you look at the 72 watt per inch Red Line we can see that the efficiency for the the um Gan is near 97.5 while for the Silicon it Still Remains at 96.7% efficiency and so while this analysis clearly shows uh the gain Advantage it is important to note that even with Gan there are limitations and Beyond a certain power density that is uh certain maximum switching frequency there will be degradation in efficiency so B Gan transistors have been in production for a while but what are the latest developments and are there any unique devices on the road map to watch for I agree and uh while improved Gan switches so far been introduced compared to the Silicon devices they are in a way similar to the existing devices so one of the latest and unique development utilizing Gan is the monolithic bidirectional switch and Inon we are on the onset of introducing two version of these monolithic bidirectional switches one which is designated on this slide as dual gate BDS is the high voltage version and the other is the single gate BDS which is the mid voltage in the range of 40 to 200 volt so the Dual gate BDS the high voltage variance this device can operate in bidirectional mode in which it can conduct current in both direction or block voltage in both direction as well or it can also operate in the DI mode when one gate is on and the other is off this device has two independent Gates as shown on the um circle on the left top it is a monolithic merger of two hemp devices which uh share the same drift region and internally the two devices share a common drain and it also features a substrate management circuit which sequences depending on the mode of operation of the device so the single gate BDS is the low voltage variance it only enables the bidirectional mode and it's also a monolithic merger of the two switches but in a common source Arrangement so overall the BDS devices will provide an opportunity to replace multiple devices of to four the relevant application leading to not only space and power loss savings but potentially cost savings as well what kind of applications can benefit from such a bidirectional switch so these are examples of immediate applications which could benefit from the use of Gan mbds devices for example in the server Market it can enable significant board savings as well as power loss savings when used as a load disconnect or in oring functions and the consumer applications highlighted on the top right for example with a continued proliferation of USB on the go mbds can serve as a load disconnect switch which can obviously conduct current in both Direction and block voltage in both Direction necessary for a USB device which allows power flow in both directions and the energy storage systems and BSM BMS systems such bidirectional switches can enable the next level of power density when used as a battery or load disconnect switches okay so being such a unique and versatile switch are there any Innovative approaches in the power electronic field to take better advantage of this kind of switch indeed uh there is a new opportunities to increase power density in existing topologies such as current Source inverters or opening the frontier to explore new topologies such as Matrix converters here on the left side is a high voltage Gan mbds driven by two independent gate drivers and corresponding aux supplies such an arrangement can replace two back-to-back silicon or silicon carbide devices in current Source inverters as shown on the top right allowing for higher efficiency and higher power density and both Academia as well as in industry has uh begun on new topologies such as uh Matrix converters which allow for a direct ACDC isolated and power factor corrected power conversion which eliminates the need for an intermediate bus capacitor for example Le with the Advent of the bidirectional switch there are opportunities to take advantage of Gan utilize new topologies to better address power conversion needs in a more efficient way and enable the next power density levels all right so to wrap things up zobe can you recap your main points for me absolutely so we reviewed and understood that G as a wi band Gap device enables uh Superior switching and conduction performance with is both silicon and silicon carbide the emote Gan is available in both Shi gate as well as the PN gate also called the gate injection transistor we understood that a unified gate driver configuration can be used to drive either shoty gate or the git gate and understanding that the Egan has a lower V Threshold at its gate is is important to mitigate undesired turn on especially during the first pulse events that be reviewed by using proper gate biasing approaches and uh for best utilization of Gan so uh capabilities it is beneficial to take advantage of flux cancellation in mutually coupled power traces to minimize power Loop inductances when we're laying out our boards with can having a superior figure of merits it enables hard switching topologies such as totem pole PFC and allows for higher switching frequencies in resonant converters such as LLC we also reviewed a parront analysis and that shows that indeed Gan enables the next level of power density but it is prudent to be cognizant of its uh limitation as well as Beyond a certain switching frequency efficiency degradation is to be expected and finally we reviewed very briefly the next available exciting devices in Gan technology the monolithic bidirectional switches that not only enable higher efficiency in existing topologies but provide an opportunity to look into more advanced topologies such as Matrix converters to further simplify and enable higher power cities excellent well I think that's all I have time for today thank you so much for joining me thank you for the opportunity to speaking with you and before we go you didn't forget to click that link did you there you can find even more information about this topic from infinion for chalk talks I'm Amelia Dalton from EEG journal.com for more chalk talks head on

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2024-12-26 06:11

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