well good morning everyone it is a sunny morning over here at mit nano and that's great to have you join us thank you very much for being here with us uh this morning uh we have an absolute pleasure of welcoming ahmad zubair as the speaker of this next nano exploration store uh he will talk to us about challenges and opportunities for the next generation of power electronic devices ahmad is a post doc at mit working with professor thomas palacios he finished his phd with thomas and billy dresslehaus and we very much look forward to hearing his talk before he starts i will remind you that you should turn off your video and mute your sound uh if you haven't already done so that will increase the bandwidth for the rest of us uh if you have any questions please feel free to send them a in a chat and we'll make sure to read them off uh beyond that uh you can at the end of the talk raise your hand and i'll call on you and we can ask any questions that you might have for him at this point i will ask ahmad to take over thank you vladimir for the kind introduction it's my great pleasure to be here today because we have been using uh mit nano facilities for all our work for many years and it's a pleasure to present the work to the community so in my talk today first i'll give you a brief introduction about vertical gan power finfet and our recent work on ganon silicon synthetic and a novel subject replacement technology that we have recently developed so first i'll uh point everyone's attention to this uh well used figure over the years to showing how the power density and the transistor count is changing in a microprocessor i would like to particularly draw everyone's attention to this figure the typical power level in a transistor microprocessor is about 100 watts and now if you want to look into the application space of power electronic devices this is a figure from a traditional textbook from 2008 and we see that the application space of various uh power electronic devices have a wider much wider range than the microprocessor expanding from 10 10 volt to 10 000 volt and from a few milliamps to 10 000 amps and if you try to plot the power level of microprocessor it just falls below here which means the affection space of power electronics in terms of voltage and current rattling has a much wider range than the any other electronic uh applications that we experience in our everyday life and that's not all recently there have been a lot of emerging application of power electronic devices we have a power electronics everywhere in our electric vehicles the inverters and the data centers and the market for the power electronics has been exponentially increasing for last decade or so and it we expect it to increase in the same fashion if not more in future however the energy efficiency of the power electronic device is the key for a better future why uh if you look at this uh plot here from the lawrence lieberman national laboratory the total generated electricity in 2019 in the u.s and bulk of it about uh has been wasted through the inefficient use and now by 2013 a significant part of the 2030 a significant part of the generated electricity is expected to flow through the power electric devices and as a result we need to have our power electronic devices as efficient as possible because we don't want to lose our energies through the just because our power electronic devices were not efficient enough so currently the power electronics market is dominated by the silicon devices on the left i have a plot where we i show the typical um performance matrix of the power electronic devices on the y axis we have the specific on resistance which determines the switching loss of the device we want every power electric device to has as lower switching loss as possible so which means we have to have a lowest are on rsp possible and on the x-axis we have the bv or breakdown voltage that determines the voltage handling capability of any power now if you plot the look at the silicon curve it's a somewhere here on the top left but due to the excellent material properties of wider band gap materials such as gallium nitride and silicon carbide we can expect much higher performance improvement in power electric devices for example we can expect more than 50 times improvement in the specific on resistance and more than 3000 time improvement in the breakdown voltage if we move from silicon to gallium nitride thanks to its wider band gap and excellent transport and material properties and in future we will also want to move the lower right hand corner with a probably a new device architecture or technology but for today's talk i'll limit my uh discussion about gallium nitride so the gallium nitride has been uh therefore out there for a while and almost all the companies now have their calibrated products in their road maps and it's continuously expanding uh over the years however uh all these galanter devices are based on a lateral geometry or what we call high electron mobility transistors on on the left i show a typical cross section image of a high electron mobility transistor of gallium made of gallium nitride here we have a source and then the drain and here we have the gate and since there's a power device to support the voltage handling capability there is a un-gated region which is in our electrons technologies called the drift region so this region is used to support the voltage handling capability so although gallium nitride hems or planar gallium needed devices are everywhere there are few drawbacks that limits us to expanded capability into in a large much wider voltage range or a current ratings first of all in a lateral geometry it's difficult to increase the current rating because the current current rating of the device depends on the total area of the transistor since the lateral geometry everything is on the surface if you want to increase the current rating we have to make the devices really big that affects the that also increases the device footprint the same problem happens and we're going to scale the voltage handling capability of the lateral devices to increase the voltage handling capability of the lateral devices we also need to increase this length of the drift region again it uh we get affected in terms of device footprint the third is actually very um very important bottleneck is the heat generation capability since the lateral geometry the transport is happening at the near the interface so which means when we are flowing a really high current the all the heaps are concentrated near the surface and the bulk of the substrate is unused and it's not helping to dissipate the any of the heats and the final problem of the lateral geometry is the non-uniform electric field in a lateral geometry electric field is concentrated at the edge of the gate and that help that makes the reliability of these devices very challenging now we can solve this problem by going vertical the primary advantage of the vertical geometry um would be the we can achieve very high breakdown voltage without enlarging chip size because now we can change that we can increase the drift region which is along the vertical direction but by just controlling the thickness of the ap layer instead of a device footprint also we can play with the geometry and achieve much higher current capability without having to impact the footprint of the device and vertical geometry also helps with the better distribution of the electric field and uniform heat generation for example if you look at the heat map of a vertical versus lateral power devices as we can see here on the top the lateral devices the heat is concentrated at the temperature of the device is very high near the surface but in vertical devices temperature is more evenly distributed throughout the substrate and if you look at this plot where in the x-axis we are showing the particular power density versus the temperature of the device we can see that at the same power density vertical uh devices offer much less temperature rise compared to the lateral counter parts so all these device all these uh advantages make us really excited to pursue the vertical devices in gallium nitride and there have been a lot of work in the community on the vertical gan transistors over the year two common uh two most common approaches was uh what um it's typically called that current aperture vertical electron transistor and the trench mosfet architecture and in both of the technologies our colleagues around the world have shown very uh promising performances with a breakdown voltage up to 1.5 kilovolt and specific on resistance down to around two mediums centimeters square so now uh this both of the approach relies on uh developing novel junction for example here we are having a we're showing a typical architecture of a vertical gan transistor where we have a p-type gallium nitrogen that helps uh to form a junction between the n-type gain and helps to confine the current however there is a fundamental problem with this uh this junction based approach because the doping of the p-type doping of the gallium nitride has proven to be very challenging and this device architecture requires regrowth and regrowth is very expensive and sometimes technologically challenging to work on these two problems our group have come out with a new approach where instead of developing a junction we use geometric confinement and nanoscale patterning to uh control the carrier flow in a vertical transistor so the beauty of this approach is we don't need any key gain and we don't need any regrowth we can just take a simple api layer structure with an n plus scan n minus scan and again uh heavy dope can substrate and just pattern it and make our transistors and that gives us a lot of design flexibilities where we can just control our process parameters and define various uh gate lengths threshold voltage and everything so it opens up a whole new design space for high voltage high power uh vertical transistor using gallium nitride using this approach a few years ago our group demonstrated 5 amps 1200 volt vertical gain power fin fit on bulk and substrate these devices showed normally of performance the threshold voltage of 1 volt on a ratio of 10 to the power 10 and 10 uh 5 amps current in an area of 0.5 millimeter square die size and not only that if you look at also the switching performance of the devices these devices show competitive performance among all the silicon carbide and silicon powered devices in terms of both current density chip area and the switching um charge and uh switching speed so now that was very promising start and all of these uh demonstrated devices were made on a native gallium nitride substrate or freestanding bulk gallium nature substrate so now let me change the topic towards why we need ganon silicon technology here so one of the primary challenges with this uh vertical gantt fin effect on bulk eliminator substrate is the scaling down of the on resistance which determines the switching loss when we did analyze this about the total resistance contribution of different components in the device we found that 70 percent 75 percent of our own resistance is coming from the substrate itself although the substrate is n plus uh gallium nitride but the contribution of the 300 micron thick substrate is a bit as the major contributor to the whole iron of the device and the second most challenging part is the technological scaling of this technology devices all these devices were made on as i said uh native gallium nitride or ganon can substrate these wafers are excellent because we can grow thick ap with very low defect density which is important for vertical devices but the wafer diameter is limited to two to four inch um and also the cost is significantly higher than any other um any traditional commercialized technology like silicon wafers on the other hand we have also option to develop this technology on traditional gannon silicon platform this this wafers can come as as large as eight inch diameter and the wafer cost is significantly lower however the defect density is a primary challenge in traditional ganon silicon wafers also that it's a it has been proven very challenging to develop thick ap layers on this uh traditional ganon silicon wafers which is required to support very high voltage devices for example here is a cross-section scm from the literature we are showing that the typical ganon silicon wafer where the dislocation density is very high and thickness is limited to avoid cracking also due to the presence of insulating and defective buffer the transport can be very challenging through this kind of structure so to overcome these problems we collaborated with a company chromis where they have a patented technology but they call this qst engineered substrate technology the key to this substrate technology is the substrate itself so in this plot we have the coefficient of thermal expansion for different substrate that can be used for gallium nitride so the red one represent the city for silicon and here this curve is for the uh gallium nitride as we can see the question of uh city mismatch between silicon and gann is really high which causes the ap to crack if you just grow directly and take ap silicon but these substrates from our collaborators they use a poly aluminum nitrate as the core and the ct mismatch between the aluminum polycrystalline aluminum nitride and gann is minimal and which helps us to develop a very thick ap without cracking or high defect density here is an example of a 30 micron thick gallium nitride grown on this custard technology and a better news is these wafers can be grown an 8 to 12 inch wafer scale so that gives us immediate uh opportunity to scale up our device technologies and fabricate in a commercial fair so motivated by this we started developing our own technology on this uh qst gannon silicon substrate couple of years ago this is our typical device flow fabrication flow which we have been doing in mit nano for many years now so our device fabrication start with the etching of the gallium nitride fins and then we define field oxide which to manage the electric field and we form the gates along the sidewall of these fins and we etch the drain and mesa and finally we do a planetarization silicon diox oxide spacer and uh pad metallization i'll explain the important steps in next few slides the first most important step in our fabrication technology is the fin formation so for the fin formation we deposit a silicon nickel hard mask through e-beam lithography and even evaporation and do a dry edge to define the fin length of pin uh in length and width and after the dry edge as we can see from this same image there are a lot of sidewall damages due to the from the dry edge to over uh since we want to have our channels across the sidewalks it's very important to get rid of these damages and get a very smooth sidewall for our subsequent ldd position and get metal patterning so to do that we align our fins with a specific crystal orientation that helps us to use a crystal plane selective weight edge and that only edges the side walls uh significantly on a very low edge cut in the other crystal planes and after a successful uh crystal pencil active weightage and cleaning of the substrate we get very nice smooth fins uh with the very excellent sidewalls and once we have the fins our next step is the gate patterning where we deposit atmosphere of the atomic layer deposition with aluminum oxide wrapping around the fins and we sputter gate metal on top of it after that we do a planarization and h-pack to define the gate length and finally we remove our planarization dielectric and then we have our fins with the gate oxide and gate metal so in the first generation of devices we were using a photoresist base planarization process the advantage of this photoresist planarization is it said it's selective because we can just etch it with a oxygen plasma however uh since it's a photoresist spin on it also depends on the process parameters and it's really hard to control so recently we have developed a pcb silicon dioxide based planarization technology which is very robust and which also has a but it also it's the edge chemistry is similar to our gate metal patterning chemistry so we'll have to optimize that the edge process to get the perfect uh eight patterning um process as an intermediate solution what we have pursued is the aluminium base a weighted space gate patterning where we use this uh theosp pcb silicon dax based planarization then we expect the silicon dioxide with a cf4 o2 chemistry and once we have the at the desired uh height for our gate length we used a wet edge to selectively etch the aluminum from the side wall and define our gate length and finally we re we use a subsequent cfo and oxygen dry edge to remove the planarization dielectric which is in this case is silicon dioxide and once we have our gate defined the next step step is uh the spacer oxide which basically separates the gate metal from the source metal which is on top to do that uh we we again use a pcbd sio2 solution and we are using a tears precursor and due to the use of kiosk precursor the silicon dioxide actually grows conformally from the side walls and once this keeps growing it actually merges the front and uh nicely planarized on top of the device and after that we can etch back and once we expose the source spin region source region of the fins we deposit our metal and finish the device fabrication and this is a cross-section uh focus and image of one of our typical fabricated device where we have the galimetric pattern fins the gate metal on the side walls the silicon dioxide spacer and the source metal on top so this uh this is the spacer layer which is separating the gate and source metal and avoid being shorted and here we are showing our typical output characteristics of our ganon silicon um finfet fabricated on engineered substrate um we are reporting a current density of around four kilograms per centimeter square if we normalize the current with respect to the fin and the spacing in between the fins however our current devices are limited by the um source contact resistance which we need uh which we will need to improve by applying few techniques in future how if we consider the total current current density flowing through each fin is actually very high it's more than 30 kilograms per centimeter square so although currently the uh normalized current density over the activator is about four kilograms per centimeter square in future we can um make the fin density higher and even um achieve a higher current rating from these devices so this current density is showing a potential for further scaling of the current rating of these devices so now if you want to benchmark where our devices stand in terms of the other gain on silicon vertical transistor and literature here on the right hand side on the plot we are showing the different technologies that our colleagues have published around the world and in our first generation of fabricated devices our current density is much higher than the any other ganon silicon vertical transistor present in the literature is a very promising result given that we have not optimized the technologies yet and that also encourages us to pursue this direction even further so now i'll talk about a novel substrate replacement technology that we have developed to further uh push the limits of these finfets on silicon substrate so in the first generation of devices we use a quasi-vertical architecture for devices where our drain layer was not at exactly in the bottom of the device we still have the qh3 substrate remaining and the buffer layer that used for growth and we etch down the drain layer and put the source layer on top of this from here so that we can probe from the top but that's not it was that's not possible if you want to do a really high voltage devices but the thickness of the drift region would be tens of microns we need to develop a technology where we can um the drain metal can be at the bottom of the substrate instead of from the top so what we want to develop in the next generation is a fully vertical architecture where we'll have our source on the top gates on the side wall and the drain at the bottom and if you want to achieve a 1200 fold rating from our experience and calculation we know that we need about 10 micrometer thick drift and to demonstrate this second generation device we have to develop a substrate removal and replacement technology we have to replace the substrate because for the mechanical stability and since the substrate resistance was the 75 percent of the total on resistance of the finfet if you remove the substrate completely it will also help us with the super um on resistance of the device and the thermal management because of the ultra thin nature and the conductive electroplated copper on the back side of the device now uh the substrate removal is very challenging because of the complicated structure of the substrate this engineered substrate itself if you look at the substrate uh if you once we are fabricating the device and this is the subject underneath if you look closely at the substrate the substrate underneath the n plus gallium nature drain has many layers such as n buffer layers 111 the engineered layers and the polycrystalline aluminum nitride core so we developed a process where we first temporarily use a temporary bonding to address the sample upside down on a carrier wafer then we grind the polycrystalline aluminum nitride from 700 micron to 50 to 100 micron thin and we use a hot koh weight edge to remove the rest of the gallium aluminium nitrate and then we use a combination of dry and wet edge to remove the engineered layers and we dry use the silicon 111 and also time dry edge the gan buffer layer to stop on the n plus train so this is a one of the example of one when we were developing the process here on the left we have this this uh sapphire carrier used for this subset removal process and this temporary bonding material hd 1011 and this is after complete suction removal we can see that ultra thin gallium nitride which is about 10 micron thick remaining on the substrate and since it's a white bandgap material it's completely transparent as we can see on the right hand side so now that we have developed the subject removal technology the next step is to replace it so that we can debond the carrier have it and have a freestanding device so to do that we start with the first our drain side contact which is typically we use uh tie aluminum we spotted the drain contact on top of the n plus scan and then we use a diffusion barrier titanium nitride and uh for electroplating we deposit uh copper as the seed layer and we electroplate 50 to 100 micron copper and finally we debond the to the bonding material and we have our free standing devices so before going into the finfet fabrication we developed the process in a simpler structure on a diode devices so the diode structure before fabric after fabrication and before substituting mobile looks like uh the one i'm showing here on the left so we have nickel gold nickel shortcake contact on the front side then we have the drift region which is about 10 micron thick and the n plus can uh bottom layer and a qst substrate and once we remove everything and replace the substrate electroplated copper this is one of our finished substrate how it looks like so here we have a freestanding galamonite shortcut diode fabricated on a 50 micron copper and if we zoom in we can see the diode patterns all over the surface and as it happened yesterday we measured our first uh fully vertical shortcut after subset replacement in the lab and this is the typical iv characteristics of the fabricated short key diode on a of a freestanding uh qst sub uh freestanding aluminum nitride from a qsd substrate on 50 micron electroplated copper we'll need to improve the device characters further by advanced engineering but this is a promising start for our fully vertical devices so uh our next step would be to fabricate fully vertical fin fit on this qs3 substrate so we are currently we have fabricated the fin fets on the substrate and now we are working on the substrate removal and hopefully in future in near future we'll be able to characterize and demonstrate the first uh first generation of the fully vertical devices with the replace the substrate so this is a very promising development that we are working on our lab but i'd also like to point out that gann has been a the heterogeneous integration of canon silicon has been out there for a while for example our group in 2012 and demonstrated lateral gain hems on a silicon substrate and a side-by-side technology over a six-inch wafer and recently intel took it to the next level and they demonstrated again silicon heterogeneous integration of a 12 inch wafer and this is these devices are being um considered for power and rf delivery and a lot of different application that wide bandgap and high mobility materials can enable so our technology is along the same line where we are trying to develop on silicon substrate that can be transferred directly into commercial fat and enable many new application in a much wider voltage range and the power capability in summary uh today i have shown that our first demonstration of quasi-vertical ganon silicon finfet on engineered qst substrate and our first generation of devices has shown promising performance and record current density among all the ganon silicon vertical transistor we have developed a novel substrate replacement technology that uh promises superior thermal management and better uh switching laws and finally we are fresh from the lab we are first fully vertical short key diode with replace substrate at this point this is the most important slide of my talk i would like to acknowledge all the people without their help the work hadn't been possible and the most important people in these slides are the graduate students were spending all their days and nights in the lab josh and john who made this technology possible and our funding uh sources uh samsung arpa-e and darpa with their generous support our research has been possible here and a lot of people from uh are collaborating cromis brevard science and different groups from mit and of course all the staff and the from the mit nano without their help nothing would have been possible and at this point i would like to thank the organizer for inviting me and i'd be happy to take any questions thank you so much for a great talk if you have any questions from ahmad and i'm sure there are many please do feel free to either raise your hand and myself or cherise will call upon you uh and secondly uh uh make sure you uh indeed send us some chat questions if that's uh uh better for you either way we're gonna try to call on you and relate your question to ahmad um yes uh we have a question from uh jung joon kim yeah thank you thank you for the nice presentation this uh one quick question so guardian nitride on the qst that structure you have deposited thai nitride before electrocopper electroplating but usually in semi area uh tandem nitride or tenon is regarded as very good copper uh diffusion barrier any particular reason why using thai nitride and then also at the very high temperature i don't know if thai nitrite can uh prevent copper diffusion into transistor area yeah the temperature is uh quite different uh from the usual semi right yeah so this carbon nitride yeah so excellent question yeah i think that um yeah as this um tantalum nitrate is the standard diffusion barrier for the that industry has been using for a while um i think uh we are still working on developing a tantalum nitride diffusion barrier right now the tools we're using uh currently we have a developed recipe for the titanium nitride and that works well for our purposes for now but in future we we plan to expand it to the 10th alumni trade and regarding the thermal budget well actually our thermal budget is limited by the stability of the dielectric on the front end of the device so we cannot from our experience so far we we saw that uh we cannot go beyond 500 celsius with the current gate technology that we have so in this uh current generation of devices our thermal budget will be limited to 500 500 degree celsius anyways so that shouldn't be a problem for now but of course in future we'll have to uh use standalone nitride and a better uh other technologies to make it uh compatible with other technologies thank you for the question uh thank you so may i give one more question of course please go ahead yeah then the the your another application saw the vertical uh structure gallium nitride and silicon uh platform so if you compare this one for example garden nitrogen silicon carbide which is a vertical uh current uh transportation so your structure the is has any benefit over that uh that uh the carbon nitride and silicon which is in here it has inherent the benefit right uh i think the inherent benefit comes from the scalability of this uh the substrate itself is now already in the eight inch and it can go into the twelve inch i mean they are working on to develop a twelve inch circuit soon i think the primary benefit is coming from that fact that we can immediately scale up for the commercial fabrication in a very large scale device demonstration in terms of cost do you mean yeah in terms of cost and also i think uh they have shown that they can grow 30 micron thick ep without uh cracking so if in future if you want to expand the voltage handling capability of these devices this technology can be proved really advantageous yes okay thank you all right um any additional questions please do raise your hand and we will call upon you or you can send them in a chat to everyone i'll do my best uh to represent your question most appropriately ahmad your uh technology is remarkable right i mean the high power electronics the high kind of currents you're able to achieve uh it is also relatively bulky let's say in comparison to a typical silicon high node transistor so the question in my mind would be what is the ultimate speed you think you could achieve with the technology as it's done right now or maybe as it will be done in the future and what is a needed frequency of response given the fact that many of these transistors would be used for power electronics that do not require extremely high frequencies um wonder if you can comment on that the speed of response yeah thank you very excellent question so you are right it's a very bulky uh if you look into the speed of the power electronics these days uh and we are still in the range of kilohertz to we're really pushing uh towards a megahertz frequency of response in the power electronics so that's where i think the uh high mobility of the gallium nitride and other materials comes into play so i think with this uh technologies we can uh when we go to the high mobility materials we can uh go to the higher frequency and the higher frequency also advantages for power electronics because it helps us to um scale down the size of the passive component such as capacitor inductor and it also helps with the form factor of the whole system for example uh i think in the in the very beginning so for example here we uh the whole module that tesla and estimator electronics developing on silicon carbide it's also already showing a significant reduction of the form factor compared to silicon technologies just because the superior transport and the mobility the material itself but i think getting a megahertz power electronics would be amazing at high voltage level for now and i think uh if you talk about high frequency high power our group is also working on uh these transistors also we are trying to optimize for high frequency hyper uh where we are targeting 30 gigahertz to higher ranges where we can develop really high power for uh different level of application not exactly for this kind of our traditional power electronics so by changing the device architecture we can go for traditional hydraulic uh power electronics with higher power capability up to megahertz probably beyond but if we change the architecture and do some device engineering can push to high power high electronics to um even uh tens of gigahertz yeah of course there's always a fundamental power bandwidth product uh limit that and and indeed it would be intriguing to consider it uh my very last question as we are running out of time uh what is the biggest challenge now from perspective of the next step is that series resistance of the source contact or is it uh the capacitance of the very large um a gate electrodes that you might be using uh is there the next obvious thing for you to tackle uh to make these devices even better yeah i think uh as you said the immediate challenge that we're really looking for to solve with the source contact resistance so right now our uh as i showed in my iv that it's not particularly great but uh we know that if we can add some uh thermal annealing without degrading the gate stack or maybe some other advanced technology that can really help to improve the performance of the device i think that's the primary direction what we are looking right now to improve the on resistance by improving the source context all right well ahmad thank you so much uh for giving us a fantastic talk um it i did receive a question in the chat on where will the talk be available it will be available on mit nano website mit nano.mit.edu you can go under the
events and seminars and nano explorations is among there and all of the previous talks are indeed all the previous talks we received permission to post and that's most of them uh are available there for your perusal this talk will be available in the next couple of weeks uh and you'll have a chance to enjoy ahmad's great talk one more time if you wish to do so at this point i would like to conclude by just simply reminding you of the upcoming nano explorations talk uh it is going to happen uh two weeks from now march 16th uh 11 a.m eastern standard time um jules stewart uh will tell us about integrated photonics and electronics for chip scale quantum control of trapped ions i hope you'll be able to join us then thank you again for being with us today take care
2021-03-30