hi everyone and welcome to another of Ian's interviews we've all been wondering what's happening with process node technology are we at a fundamental limit if we look at the road maps of the leading uh proex technology manufacturers today they'll tell you that they've got road maps going out on and on and on so the question is is moors Lord dead or is it still alive we've seen the Advent of chiplets and integrated packaging become this new wave of AI technology to enable what is going to be the future of compute whether that's high performance Computing machine learning Automotive or everything else joining me today is Dr Kevin Zang SVP of tsmc a wellknown well regarded industry veteran thank you for joining me on the channel pleasure so my first question is that if I go and look at some CEOs giving presentations they talk about how Moos law is dead the fact that they have to innovate on architecture because they're not getting much from packaging and process node Technologies I speak to other people and they say oh no MN still alive we've got you know road maps to 2036 where's tsmc's position on this well I think my simple answer is I don't care as long as we can continue to drive the technology scaling I don't care mlaw is alive or dead but you know reality is lots of people narrowly Define morow b based on two-dimensional scaling uh that's no longer the case if you look at the Innovation hen in our industry we actually continue to find a different way to integrate a more function a more capability into the small form factor continue to achieve higher level performance and a higher level of power efficiency so from that perspective I think most law or technology scaling will continue we we will continue to innovate to carry the industry forward so should we redefine Mo's law should we have a new law that I leave somebody else to Define yeah so tsmc is known for being very incremental with its process node updates you'll have a major process node and then minor variations that iterate on a theme to improve power performance dty before jumping forward with a new family of process noes um how much of tsmc's success would you attribute to this incremental strategy because we're seeing foundaries do both right we seeing foundaries do both the big jumps we've got a couple of big jumps coming up in the industry but tsmc seems very adamant on this you know s of slower Cadence well I don't particularly like the word incremental if you look at our technology road map you know from 5 NM to 3 NM nor for 3 NM to 10 2 NM if you look at energy efficient Improvement it's not incremental over 30% per generation but in between the major node we are continue to drive the incremental enhancement the reason we do that is we allow our customer to continue to harvest each new generation of technology in term of a scaling benefit so between major node yes we continue to drive the incremental but between the major note actually the enhancement or the power performance density Improvement is very substantial so is is that because when a customer goes into a major node they obviously have a lot of upfront cost to develop the chip and then using those you know updates to that major noes they can leverage the same similar or at least similar designs rather than spending a big bucket of money correct correct for example 59 met right after uh our customer M to 5 NM they can continue to Leverage The incremental enhancement from N5 to n5p when you get the Prof uh uh the performance boost then you go to N4 n4p you can further dens the Improvement so those incremental enhancement after you jump on the major note allow our customer continue to harvest the scaling benefits and the investment they make upfront so how many of those sort of enhancements to a major node end up coming from you know internal you know outbound design versus inbound customer demand do do you end up you know having a customer saying I want you I need you to do this can you do it on this process node and then having to go solve that well uh you know we uh work very closely with our customer to pick the right uh technology note to intercept their product this is a often based on specific product design to see where they can most achieve their Optimum device level the product level benefit so we work very closely with our customer to make like right choice yeah have you had any surprising requests from customers no I we don't want surprise customer we actually uh work very closely very open with our customer to make sure they choose the right technology remember we are in a Foundry business model our goal is really to help customer to achieve successful product uh my boss often tell me uh Kevin you know we're in The Foundry business we work together we achieve success but there is a sequence customer has to succeed first then we can be successful okay um so to that point we're here at tsmc's EU Tech Symposium you've just had the US Symposium there's a few going around around the world and the major announcement or the two major announcements I guess is a new major node A6 and this new super power rail technology also coming in with that generation what do these bring to the table yeah yeah so you know a16 is a major technology enhancement or revolutionary in term of bring further power performance to Future high performance application especially targeting for HPC and AI uh a16 feature uh Nano sheet transistor which is the industry leading most advanced transistor archit texure but the same times we add a very Innovative backside Power Wheel Design This back backside power re design allow uh design uh customer to move the power supply uh routing from the front to the back open up space allow to enhance the performance same times improve the power supply this is a particularly important for very high performance system design because power delivery has become very very important critical we talk about in a small form factor you have to bring close to a few hundred Watts so the IR droop become very very significant by moving the power reel to the back side you actually significantly improve the Integrity of the power supply reel our uh approach is very different from the conventional design the conventional backside power reel basically you just drill a hole connect the backside metal to the front side metal you burn space right you you have to enlarge the footprint of the library cell but in our design we have very Innovative approach entually we move the contact of transistor the source of the transistor to the back without changing the footprint of the library cell so this clever way allow us to maintain the footprint provide the maximum flexibility to our customers does that mean that the traditional manufacturing steps go a little bit out of order in order to enable that uh I want to get into this specific process step because our Rd our Rd team will not be very happy yeah um but it is very much you know a sandwich design transistors signal power um Sur you that adds that would add a lot of cost to the manufacturing definitely definitely will have a cost associated with but if you look at the density power performance benefit I think it's outweigh the cost this is a particular important for HPC and AI application where energy efficient compute is the king is the driver yeah so if somebody goes forward and chooses uh the a16 node do they have to take the super power power rail with it uh a16 uh by definition will have the backside po we call Super Power Ra yes okay that's good but we do offer the technology option allow a customer continue to leverage uh the existing design uh uh collateral uh don't have to use the backside power for example for mobile uh application you don't where the power supply uh Power routing is not as intense you don't have to use the the backside Power Wheel so normally at these events whether it's you or your competitors the announcement comes a few years before production so so where where in the timeline are we expecting a16 and super we're targeting second half of 2026 going into production for our a16 for for the lead customers and Y um so does that mean you're sort of like version 0.1 in the pdk right now or uh how does that work well I don't think uh uh I want to get into detail into C collateral schedule but in general our collateral schedule is designed to Target the customer uh production days uh introduction as we said earlier uh we target a16 going to production by second half of 20 uh 26 so our colloud schedule will support like kind of schedule and we're expecting this all to be manufactured in Taiwan and C you uh a16 will start in Taiwan yeah yeah one of the other announcements at the show is actually something I find really impressive because last year you introduced This this term called fin Flex the ability to take um N3 and and sort of reduce the FY population to decide whether you wanted high performance or high efficiency and now you're doing this nanolex with N2 and you fin Flex nanoflex it's quite easy to see where you got the name from um but how does nanoflex differ to what we understand with flex yeah uh yes this is a very Innovative approach you probably heard about Design Technology co-optimization dtco dtco this is where we continue to uh Drive the collaboration between design and technology in order to further optimize our technology offering to provide a better scaling benefit so uh fin flx you mentioned earlier because in a fin transistor architecture the number of fin is digitized so in the past before this Innovative fin Flex approach you have to use either three fin or four fin um you can't swap them easily so our fin Flex technology at a 39 M allow designer to mix and match different fin uh based uh uh Library design but for the a nano sheet we call nanox this is effectively similar idea allow the designer to mix match different height of the library okay different sheet width based on the LI sheet width so you can uh alternate uh different size different height of Library allow design to choose and pick based on specific design Target to achieve Optimum benefit in of power performance and density yeah very Innovative approach so it it's still three sheets High which is seems to be an industry standard for yes but you can vary the sheet WIS yeah which determine the height of the library then that obviously means you have different VT characteristics based oning that's on top that's a dogal to the to the height of the library so so you can go nanoflex and VT yeah yes you do have a lot of options as a designer you're going give too many options out I think that's could be a problem Yeah Yeah pivoting from that onto packaging um it you know I'd be remiss if I didn't mention the fact that tsmc right now if I can't mention packaging without saying tsmc Coos in the same sentence people get mad if I don't say Coos um and I know Coos is in high demand we only have to look at you know Nvidia AMD Intel um or or look at the broad sheets to see that this is being talked about actively in terms of where you guys are on um being able to supply what the market needs um how is expansion of Coos progressing uh first thing first Kaa is today is the work force Workhorse for AI accelerator if you look at all the AI accelerator design pretty much today they all base on tsmc 5 NM or 4 NM technology plus Co-op coas is in high demand everybody can spell coas this St even the TV reporter can do that so uh obviously last year uh the AI Sur took a lot of people including ourself by surprise the coas demand uh has surged tremendously over last year we are uh rapidly expanding our coart capacity now uh I think uh the K girl we're talking about well about 60% uh very very very high but still uh the demand continue to grow we work with very uh very closely with our customer to uh make sure we provide their most critical need yeah but that's the capacity side coas in term of capability we're also expanding our coas capability if you look at today's state of Arts AI accelerator the coas uh in poolar size roughly about 3x of the radical size radical size about 800 mm Square so that provide the capability to integrate a full radical size so along with up to 8 hbm but in the future just two years from now we will have the ability to expand the interpod size to 4.5x of the uh the the radical size allow our customer to integrate up to 12 hbm uh we're not going to stop there our Rd team already started expanding the COA in proty beyond that to s 8X of the radical size so very exciting area yeah it's 12 12 HPM is enough I keep hearing that people want more people want more so that's actually this Symposium we also announce uh another uh Innovative system level integration technology we call system on wafer essentially you think about it the maximum size you can do in a wafer processing facility is a wafer it's a 300 mm wafer so we take the wafer as our Bas layer we can bring all the logic and highb with Dam together to integrate along the wafer uh the whole wafer area so this if you measure using coas term the the number of uh X of inol size it is factly give you 40 x of the in size so humongous so this is really provide our customer to continue to integrate more compute function more memory bandwidth to address future AI requirement So speaking to that sort of wafer scale it's it's it's very well known that there are you know two main companies looking at wafer scale today and they both use you um it's uh how how much do you assist with the customers on say when it comes to you know Cooling and power management on that side does tsmd do any of that uh we work very closely with a customer so we do waer level integration and the customer obviously have to design the back end mhm the system level in term of how to bring the cooling into the system it obviously involve lots of collaboration we work very closely with our customer and the system uh uh uh provider to basically work together to find the optimal thermal solution this system on wafer it's to 2026 27 well we already have a limited production but uh in the future uh as you pointed out you know there there there are going to be more AI high performance uh customer want to leverage L level integration to address their future needs yeah and I I do have to ask you you're speaking about you know uh 3x radical 4.5 times and 40 times um in the future when reticle sizes have to get smaller due to the technology are we going to be saying are we going to have to double that number I hope we don't have to reduce the radical size because what we see is people want to IND G them all function closely together yeah so does does this mean when we're going you know getting more efficient um process node technology the demand for compute power is always increasing um you've now we're now wafer scale level packaging where's the limit sky is the limit sky the limit I I think we continuous to see the trend uh the demand for energy efficient computer it's just inable right we're talking about the AI model CH gbt model chbd uh four already use a triling variable in the future even more so think about the computation requirement it's amazing uh so we continue to expand our capability transistor level obviously we have 39 M uh next year we're going to 29 meter then we have a16 we continue to drive the energy efficient compute at the transistor level same sometimes we talk about coas expand and wafer level integration I think putting all this together by the way we also bring the optical signaling into the package right so putting all this together really we're talking about provide customer a platform allow them to integrate more compute function you know more uh uh memory bandwidths alog together to address the future AI requ requirements so it's interesting youve order Optical cuz I've actually had a you know a new customer come on board who is Optical and for some reason suddenly all these Optical companies want to speak to me about their Optical Solutions and about and about the future um the future of how that applies in high performance compute but also machine learning um how usually when I speak to those companies they're dealing with your competitors on the optical side um but you guys guys have been doing optical for a while and you've got this new new technology I want to call it Coupe because I'm British but Americans call it a coup coup so it's compact Universal Optical engine yeah Stanford that's how C Stanford yeah yeah so uh we have been uh doing silicon photonis for quite some time actually uh we uh fabricate components and our customer put the Silicon photonics together with electrical transceiver to form the So-Cal Optical uh plugable transceiver has been widely used in data center but what we're doing today is we take one step further leveraging our most advanced 3D stacking technology we call soic essentially using the hyrun technique to bring the electronic die and photonic die closer together to form a small F Factor Optical engine that's where you basically do the electron Photon conversion we know electron is good at compute but photon is better when talk about the signaling so by building this compact uh Optical engine then we integrate into the advanced packaging whether it's today's probably the substrate in the future could leverage something like a coas to bring them together to significantly improve the bandwidth and power efficiency if you look at today pure copper all electronic system the switch 50 terab switch it burn over 2,000 Watts by using this tiny um small foam Factor Optical engine we actually can bring the power down by at least 40% so this is a very very efficient in term of achieve High data bandwidth at the lowest possible power so you'll end up with some customers who want wafer scale and some who want to go Optical and yeah I think the key is to bring them together because the field it still has to be done by electron yeah yeah yeah yeah um so in that space I do see some companies talking about because you're talking about having two separate chips the electrical and the optical and bonding them together with with your most advanced hybrid bonding technology that's right um some companies are saying we actually want all of that on the same chip is that something yeah uh it's difficult to mix a photonic uh feature on the advanced uh electronic die it's difficult to do a monolithic I think by using our uh hyro bonding Technique we achieve the kind of connectivity power efficiency like almost like a monolithic but same sometimes allow us to op optimize the electronic D and the photonic die separately I think this is you get the the best of the both sides of the wars yeah you spoke about pluggable transceivers you know for the networking but obviously what we're talking about here is more about integrated photonics direct die to die into the package yeah what about pluggable version of that the plugable vers today actually if you look at the data center today uh the prevailing way to do this is using plugable at the Bor level yes so you convert uh from electron to Photon at a B level so in the future you convert within die so the signal coming after the already you turn electron to Photon yeah so that's where you get the efficiency yeah but but but will that ever be pluggable uh it is a plugable the optical the fiber plug into your D yeah but you don't want to take it out you want to leave it in if it's in it's in it's in um it'd be remiss if I didn't bring up the fact that um I very recently went on a Fab tour to see the latest and greatest from asml this sort of new high Anda Next Generation euv technology and uh the company who was there is Intel you know they're very forthright in talking about this technology and the fact that they want to be the first to deploy it um if I have you on the channel I just have to bring up the question um because there are some you know variable responses from tsmc or quotes in the Press about where you guys stand on this sort of high Anda technology um given what we've said about you know industry leading and new packaging uh and Manufacturing Technologies where are you standing on high well maybe let step back uh let's don't forget tsmc is the leader in term of bringing euv into high volume manufacturing back to our 76 nanometer generation we the very first in the industry to bring euv to a high volume manufacturing environment I think we're still the leader today in term of product uh uh euv use of UV and production efficiency uh I think our Rd team will continue to uh look at it uh the new euv capability including obviously high euv and we're going to pick the right place to intercept our technology node there are lots of factor you have to consider right there is uh there obviously the scalability uh Factor there is also a cost uh manufacturability Factor so I trust our Rd team will make the best decision where to choose the Next Generation eue to intercept our future uh technology yeah and I I I guess on that front as well um there are also discussions about you know expanding worldwide production you know trying to keep it more distributed rather than you know the single area in Asia um you guys have announced multiple Fabs around the world how's that progressing it's progressing very well and very fast too if you look at our manufacturing footprint it has expanded quite significantly just over last few years obviously you uh see we are expanding quickly in Arizona side all right we build the first Fab uh focusing on 4 neter which we're going to production next year uh and then we are uh building the second Fab there and also we are announced phase three the third Fab there so we're going to continue to bring the most leading note uh Advanced note to North America that's where our largest customer base right from 49m to 39m down to 29m or even 816 in the future right so uh that's very exciting and the same times uh we're expanding our specialty technology in both Japan and here in Europe right here in Europe right Japan the Kumamoto project has gone very well uh we're going to uh produ ction uh I I believe second half of this year yeah oh that's good yeah yeah so um we're going to bring most advanced MCU embedded non volatile memory which is very important for Auto industry here in Europe to the hard land of the Euro Zone yeah yeah um does does that extend to packaging in any way uh packaging uh we are evaluate option but the same times I think right now we uh we working closely with our partner to uh bring up the capability manufacturing capability in us maybe in the future in other places yeah I guess one other topic I want to bring up is because we're sping about Ai and machine learning right this crazy high demand um are you seeing that uh tsmc or you know through a customers that the R&D is pivoting more to catering to those customers because they're in such high you know they're so demanding they want it all tomorrow right well I think yes AI is becoming uh I think one of the major technology platform where you consume the most advanced silicon but don't forget mobile mobile continue to be uh a large volume Runner and also uh mobile require most advanced technology so we are addressing all the needs we optimize uh technology for different application different segments so our R&D work very closely with uh uh different customer different application so I think this is something very exciting um we are continue to uh Drive our technology customization to address the future uh product needs yeah so I mentioned that you know it's the Symposium here in Europe what conversations are you expecting to have today and tomorrow well uh aside from me we want to hear customers we want to uh hear what they would need in the future for their product uh fungry business is very very important to uh work closely with customer we we want hear what customers expectation and their product needs and so we can develop the right technology uh to address our customer need F business is a it's business a service business it's very very important to connect all always stay connect with your customers yeah that's awesome well good luck thank you yeah it's a pleasure pleasure talking to you yeah [Laughter] [Music]
2024-07-30